Abstract: A signal generation circuit is disclosed according to an embodiment of the invention. The signal generation circuit includes a phase control circuit, a bias control circuit and a phase interpolation circuit. The phase control circuit is configured to generate a phase control signal according to a phase adjustment signal. The bias control circuit is configured to generate a bias voltage according to the phase control signal. The phase interpolation circuit is configured to generate a clock signal according to the phase control signal and the bias voltage. The bias voltage is used to adjust a current of the phase interpolation circuit to correct an error of the clock signal.

Abstract: A data writing method, a memory controlling circuit unit and a memory storage device are provided. The method includes: receiving data; determining whether the data is compressible; when the data is compressible, writing the data into a first type of the physical erasing units; and when the data is incompressible, writing the data to a second type of the physical erasing units.

Abstract: An equalizer circuit, a memory storage device and a signal adjustment method are disclosed. The equalizer circuit is configured to receive an input signal, a reference voltage signal and a sensing clock signal and generate an error signal. The equalizer circuit is further configured to generate a first adjustment signal and a second adjustment signal according to the error signal. The equalizer circuit is further configured to update a control code from a first control code to a second control code according to at least one of the first adjustment signal and the second adjustment signal and generate an adjustment control signal according to the control code. The equalizer circuit is further configured to generate a feedback control signal according to the adjustment control signal to restore the control code from the second control code to the first control code.

Abstract: A phase-locked loop circuit calibration method for a memory storage device including a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The method includes: receiving a first signal from a host system; generating a jitter signal by the memory storage device; generating a second signal according to the first signal and the jitter signal; performing a phase-lock operation on the second signal to generate a third signal by a phase-locked loop circuit; and calibrating an electrical parameter of the phase-locked loop circuit according to a variation of a time difference between the first signal and the third signal.

Abstract: A memory control method, a memory storage device, and a memory control circuit unit are disclosed. The memory control method includes: performing a first write operation to write first data to a first physical unit in a first physical group through a first channel; performing a limited data collection operation to collect second data, wherein the limited data collection operation limits that the second data does not include data to be collected from the first physical group after the first write operation is completed; and performing a second write operation during a period of performing the first write operation, so as to write the second data to a second physical unit in the second physical group through a second channel. In addition, the limited data collection operation and the second write operation are configured to release at least one spare physical unit.

Abstract: A signal receiving circuit is provided. The signal receiving circuit includes a receiving circuit, an adjustment circuit and a boundary detection circuit. The receiving circuit is configured to receive an input signal. The adjustment circuit is configured to adjust the input signal. The boundary detection circuit is configured to detect a first signal having a first data pattern in the input signal and a second signal having a second data pattern in the input signal. The boundary detection circuit is further configured to detect a gap value between a first signal boundary of the first signal and a second signal boundary of the second signal to reflect a status of the adjustment circuit.

Abstract: A memory control method for a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The memory control method includes: determining a first management unit as a source block and reading valid data from a first continuous data unit in the first management unit according to first interleaving information and second interleaving information, wherein the first interleaving information reflects a total number of the first continuous data units in the first management unit, and the second interleaving information reflects a total number of second continuous data units in a second management unit; storing the valid data into a recycling block; and erasing the first management unit.

Abstract: A memory management method for a memory storage device including a rewritable non-volatile memory (RNVM) module is provided. The memory management method includes: receiving a plurality of commands; detecting a power glitch; and sending a command sequence which instructs the (RNVM) module to perform a first operation according to a first command among the plurality of commands and to ignore a second command among the plurality of commands after the power glitch occurs. A command queue may be scanned, and scanning may be suspended and the command queue resumed if a first-type command, such as an erase command or a write command, is found, or scanning continued if a second-type command, such as a read command, is found. A memory control circuit unit may proceed with a programming operation if it determines a write command is a non-full sequential programming command. Other commands may be suspended after a programming operation is completed according to a specific mark in a full sequential programming command.

Abstract: A cold area determining method, a memory controlling circuit unit, and a memory storage device are provided. The method includes: recording a plurality of logical update counts respectively corresponding to a plurality of logical units; calculating a plurality of reference update counts respectively corresponding to the plurality of physical erasing units according to the plurality of logical update counts; calculating a reference value according to a plurality of first logical update counts respectively corresponding to a plurality of first logical units; and determining at least one first physical erasing unit belonging to a cold area among the plurality of physical erasing units according to the reference value and the plurality of reference update counts.

Abstract: Exemplary embodiments of the disclosure provide a memory management method for a rewritable non-volatile memory module including the following steps. A host write operation is performed to receive a write command from a host system and store a first data corresponding to the write command to a first physical unit. A first updating data corresponding to the host write operation is recorded. A data merge operation is performed to read a second data from a second physical unit and store the second data to a third physical unit. A second updating data corresponding to the data merge operation is recorded. A management information is read from the rewritable non-volatile memory module to a buffer memory and updated in the buffer memory according to the first updating data and the second updating data.

Abstract: A signal generation circuit is disclosed according to an embodiment of the invention. The signal generation circuit includes a phase control circuit, a bias control circuit and a phase interpolation circuit. The phase control circuit is configured to generate a phase control signal according to a phase adjustment signal. The bias control circuit is configured to generate a bias voltage according to the phase control signal. The phase interpolation circuit is configured to generate a clock signal according to the phase control signal and the bias voltage. The bias voltage is used to adjust a current of the phase interpolation circuit to correct an error of the clock signal.

Abstract: A memory interface circuit, a memory storage device and a configuration status checking method are provided. The memory interface circuit is configured to connect a plurality of volatile memory modules and a memory controller. The volatile memory modules include a first volatile memory module and a second volatile memory module. The memory interface circuit includes a first interface circuit and a second interface circuit. The first interface circuit is configured to receive a first signal from the first volatile memory module and transmit a second signal to the second interface circuit through an internal path of the memory interface circuit. The second interface circuit is configured to transmit a third signal to the second volatile memory module according to the second signal to evaluate a configuration status of the memory interface circuit by the third signal.

Abstract: A control method of a memory storage device is provided and includes: detecting a first signal stream controlled by a host system; executing a boot code according to the first signal stream and entering a boot code mode; and receiving a command from the host system in the boot code mode and not executing a firmware code stored in a rewritable non-volatile memory module in the memory storage device. According, operational flexibility of the memory storage device may be enhanced.

Abstract: A data storing method, a memory controlling circuit unit and a memory storage device are provided. The method includes: receiving a first data; determining whether a wear degree value of a rewritable non-volatile memory module is less than a threshold; if the wear degree value of the rewritable non-volatile memory module is less than the threshold, storing the first data into the rewritable non-volatile memory module by using a first mode; and if the wear degree value of the rewritable non-volatile memory module is not less than the threshold, storing the first data into the rewritable non-volatile memory module by using a second mode. A reliability of the first data stored by using the first mode is higher than a reliability of the first data stored by using the second mode.

Abstract: A data writing method, a memory control circuit unit, and a memory storage device are provided. The method includes: receiving a first sub-data of a plurality of sub-data of a first data and generating a first error detecting code corresponding to the first sub-data; receiving a second sub-data of the plurality of sub-data of the first data and generating a second error detecting code corresponding to the second sub-data; combining the first error detecting code and the second error detecting code to obtain a third error detecting code, wherein the third error detecting code is used to check whether a second data formed by combining the first sub-data and the second sub-data has an error; and storing the second data and the third error detecting code into a rewritable non-volatile memory module.

Abstract: A memory control method for a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The method includes: reading a first physical unit based on a first read voltage level to obtain first data; reading the first physical unit based on a second read voltage level to obtain second data; reading the first physical unit based on a third read voltage level to obtain third data; obtaining a first reference value which reflects a data variation status between the first data and the second data; obtaining a second reference value which reflects a data variation status between the first data and the third data; reading the first physical unit based on a fourth read voltage level to obtain fourth data according to the first reference value and the second reference value; and decoding the fourth data by a decoding circuit.

Abstract: A data access method, a memory control circuit unit and a memory storage device are provided. The method includes generating a first error correction code corresponding to received first data according to a first error correction encoding operation; and generating a second error correction code corresponding to received second data according to a second error correction encoding operation, wherein the second error correction code includes a first and a second partial error correction code. The method further includes writing the first data, the first error correction code and the second partial error correction code to a data bit area and a redundant bit area of a first physical programming unit respectively; and writing the second data and the first partial error correction code to the data bit area and the redundant bit area of a second physical programming unit respectively.

Abstract: A voltage identifying method, a memory controlling circuit unit, and a memory storage device are provided. The method includes: reading a plurality of first memory cells according to a first read voltage group in a plurality of read voltage groups and performing a first decoding operation to generate first verification information; identifying a plurality of second read voltage groups in the plurality of read voltage groups corresponding to a first interval in a plurality of intervals according to the first interval in which the first verification information is located; and reading the plurality of first memory cells by using a third read voltage group in the plurality of second read voltage groups and performing the first decoding operation.

Abstract: A memory interface circuit, a memory storage device and a signal generation method are provided. The memory interface circuit is configured to connect a volatile memory module and a memory controller. The memory interface circuit includes a clock generation circuit, a first interface circuit and a second interface circuit. The clock generation circuit is configured to provide a reference clock signal. The first interface circuit is configured to provide an address signal to the volatile memory module based on a first transition point of the reference clock signal. The second interface circuit is configured to provide a command signal to the volatile memory module based on a second transition point of the reference clock signal. The first transition point is one of a rising edge and a falling edge of the reference clock signal. The second transition point is the other one of the rising edge and the falling edge of the reference clock signal.

Abstract: A signal receiving circuit, a memory storage device and a signal receiving method are provided. The signal receiving circuit includes an equalizer module, a clock and data recovery (CDR) circuit and a controller. The equalizer module is configured to receive a first signal and compensate the first signal to generate a second signal. The CDR circuit is configured to perform a phase locking on the second signal. The controller is configured to open or close a signal pattern filter of the CDR circuit according to the second signal, wherein the signal pattern filter is configured to filter a signal having a specific pattern in the second signal.