Abstract: An improved receiver architecture is disclosed comprising a latching mechanism coupled to receive a data stream, and a signal generator for generating latching control signals for controlling the operation of the latching mechanism. The signal generator generates one latching control signal per data period of the data stream, with each latching control signal coinciding approximately with the midpoint of a corresponding data period. The signal generator generates the latching control signals based upon a reference signal, which in one embodiment, coincides approximately with the midpoint of a data period of the data stream. The receiver may further comprise an adjustable delay element and a delay adjustment control. The adjustable delay element receives a clock signal and imposes a variable delay thereon to derive the reference signal used to generate the latching control signals. The magnitude of the variable delay is controlled by the delay adjustment control.

Abstract: A system including a failsafe mechanism adapted to visually display frame locked digital image data and a method therefor. The system receives input image data at an input frame rate and/or input resolution. The packing circuit generates coded image data by compressing the input image data. An unpacking circuit decompresses the coded image and provides output image data to a display device at an output frame rate and/or output resolution.

Abstract: The invention describes a system including a failsafe mechanism adapted to visually display frame locked digital image data and a method therefor. The system receives input image data at an input vertical refresh rate and displays the image data at a vertical refresh rate that is a predetermined fraction of the input vertical refresh rate.

Abstract: A projector determines horizontal and vertical tilt angles. Using the tilt angles and the inherent properties of the projector, keystone correction corner points for the image can be computed. The keystone correction corner points can be used to perform keystone correction on the image.

Abstract: An image processing circuit includes a processor that receives an encoded portion of a first version of an image. The processor decodes this encoded portion directly into a decoded portion of a second version of the image, the second version having a resolution that is different than the resolution of the first version. Therefore, such an image processing circuit can decode an encoded hi-res version of an image directly into a decoded lo-res version of the image. Alternatively, the image processing circuit includes a processor that modifies a motion vector associated with a portion of a first version of a first image. The processor then identifies a portion of a second image to which the modified motion vector points, the second image having a different resolution than the first version of the first image.

Abstract: The invention provides a system and method for providing a variable character size in an on-screen display application. The system includes logic means and a font memory means adapted to store a plurality of bitmaps corresponding to a plurality of characters. A mapping memory means is adapted to map the plurality of characters into the plurality of bitmaps. And a display means is adapted to display the plurality of bitmaps responsive to the logic means. The mapping memory comprises a width and a height associated with each of the plurality of characters. The mapping memory comprises a pointing means adapted to store an address associated with each of the plurality of bitmaps.

Abstract: The invention relates to a keystone correction system and method. The system includes a projector for projecting an image on a projection surface and a platform to allow a user to vertically rotate the projector before horizontally rotating the projector. The projector corrects for keystone distortion responsive to the projector's vertical and horizontal position. The platform increases the keystone range of the projector. The keystone correction method includes moving a projector in a vertical direction and moving a projector in a horizontal direction after moving the projector in a vertical direction.

Abstract: A system and method is provided for aligning multi-channel coded data over multiple clock periods. Data is received through a plurality of data channels and stored in a plurality of latches or queues. Data is scanned to determine whether a valid data transition has occurred. Once a valid transition is detected on all of the plurality of data channels, data is substantially simultaneously read out of the latches or queues resulting in synchronized or aligned data being provided at the output.

Abstract: The image scaling memory system of the present invention eliminates the use of internal or external line memories by using an existing frame memory coupled with an input buffer and a plurality of output buffers for providing a vertical scalar with simultaneous parallel access to multiple lines of data. Additionally, the image scaling memory system of the present invention, including the frame memory, is embedded into an integrated circuit. Thus, the image scaling circuit of the present invention improves reliability, lowers cost, and improves silicon area usage. The frame memory is coupled to an input buffer at an input side and a plurality of output buffers at an output side. The plurality of output buffers is positioned between the frame memory and the vertical scalar. Each output buffer sequentially gains access to and transfers portions of image lines from the frame buffer. Each output buffer stores only a portion of an image line resulting in relatively small output buffers.

Abstract: A digital video camera is coupled with an image processing station by a tether that has a bandwidth. The processing station has a memory with a program that executes instructions. When application software on the station requests a driver on the station to operate the camera at a specific frame rate, the program determines whether the requested frame rate is higher than permitted by the tether bandwidth. If that is so, the program computes a maximum permitted frame rate and an integration time of the pixels of the camera. The integration time causes the camera to produce output video frames at a rate commensurate with the computed bandwidth constrained frame rate, instead of the requested frame rate. The program then adjusts the gain accordingly.

Abstract: A multi-link receiving mechanism (MRM) is disclosed comprising a plurality of receivers. Each receiver receives a separate data stream, and all receivers receive the same clock signal. The data streams may arrive at the MRM out of alignment relative to each other (i.e. may have inter-pair skew), and the clock signal need not be aligned with any of the data streams. In response to the clock signal and the data stream, each receiver delays the clock signal by a variable delay to derive a reference signal. This is done to achieve a desired relative alignment between the data stream and the reference signal. Once the reference signal is derived, it is used by the receiver to generate a plurality of latching control signals. These latching control signals are thereafter used by the receiver to latch all of the data units of the data stream. Data from the data stream is thus recovered. Each of the receivers operates in the manner described to recover data from each of the data streams.

Abstract: A system and method are provided for calculating a target pixel for scaling an image comprising a plurality of source pixels. A contour is determined in the image using at least one of a first set of predetermined parameters. A filter tap configuration is adaptively selected from a predefined set of filter tap configurations in accordance with the determined contour. The predefined set of configurations includes a plurality of non-linear filter tap configurations. The target pixel is calculated by selectively convolving ones of the plurality of source pixels along a locus of the selected filter tap configuration with a weighting factor, and combining the convolved pixels.

Abstract: An adaptive filter calculates a target pixel from an interlaced video signal. The video signal comprises a plurality of frames, each of which comprise an even and an odd field. The filter comprises a quantized motion calculator and a filter selector. The quantized motion calculator estimates an amount of motion about the target pixel. The filter selector selects a filter in accordance with the estimated amount of motion. The filter applies a first weighting factor to a plurality of current field pixels and a second weighting factor to a plurality of previous field pixels for creating the target pixel.

Abstract: Fuzzy logic based system and method for 3:2 pull-down film mode detection that detects whether a stream of NTSC video fields originate from film source via 3:2 pull-down technique. Fuzzy logic is used to generate a reference sequence of symbols from the stream of NTSC video fields. This reference sequence is adapted for indicating whether or not the video fields originate from film source.

Abstract: A system including a failsafe mechanism adapted to visually display frame locked digital image data and a method therefor. The system receives input image data at an input frame rate and/or input resolution. The packing circuit generates coded image data by compressing the input image data. An unpacking circuit decompresses the coded image and provides output image data to a display device at an output frame rate and/or output resolution.

Abstract: The image scaling memory system of the present invention eliminates the use of internal or external line memories by using an existing frame memory coupled with an input buffer and a plurality of output buffers for providing a vertical scalar with simultaneous parallel access to multiple lines of data. Additionally, the image scaling memory system of the present invention, including the frame memory, is embedded into an integrated circuit. Thus, the image scaling circuit of the present invention improves reliability, lowers cost, and improves silicon area usage. The frame memory is coupled to an input buffer at an input side and a plurality of output buffers at an output side. The plurality of output buffers is positioned between the frame memory and the vertical scalar. Each output buffer sequentially gains access to and transfers portions of image lines from the frame buffer. Each output buffer stores only a portion of an image line resulting in relatively small output buffers.

Abstract: A CMOS output cell with multiple output modes is disclosed. In one embodiment, the cell drives a differential output signal on two output pads in one mode and two single-ended output signals on the two output pads in another mode. Differential and single-ended driver transistors are included for this purpose. A logic circuit disables unused driver transistors, and supplies appropriate drive signals to those transistors for each mode. When disabled, the driver transistors serve an electrostatic discharge (ESD) protection function, at least partially alleviating the need for ESD-specific devices in the cell. The diminished need for ESD-specific devices allows the cell to offer a highly flexible chip interface, with little or no increase in circuit area over a conventional cell that offers only single-ended or differential output.

Abstract: The present invention is an on-chip termination circuit designed to address resistance variability by making a portion of a termination resistance a MOSFET transistor operating in the triode region and replicating the termination resistance inside of a feedback loop to control the resistance of the termination resistance through the replication resistance. The MOSFET transistor's non-linear operation is mitigated by the addition of a linear resistor in series with the MOSFET transistor. By doing so, a substantial portion of the voltage across the composite termination resistance is across the linear termination resistor thereby significantly reducing the non-linear effects of the MOSFET transistor. The on-chip termination circuit includes a termination resistance, a replication resistance coupled to the termination resistance and adapted to replicate the termination resistance, and a feedback circuit adapted to maintain substantially constant a reference voltage across the replication resistance.

Abstract: An image scaling circuit for increasing or decreasing the size of a sampled image to match a fixed resolution display. The circuit includes means for resizing the image in the horizontal and vertical dimension using independent sample rate converters. The sample rate converters increase or decrease the image size by a factor of Lx/Mx in the horizontal dimension and Ly/My in the vertical dimension where Lx and Ly are integers and Mx and My are decimal numbers of arbitrary precision to provide fine scaling control. In addition, image warping is conveniently implemented by varying the down sample ratios Mx and My on a pixel by pixel and/or line by line basis.