Abstract: An optical fibre splice assembly having a pair of spigots and a sleeve, the sleeve having an internal bore of dimension large enough to permit retraction of the sleeve over at least one of the spigots, each spigot having a bore to accomodate an optical fibre adapted to be secured to an optical fibre cable through its coverings. A method for producing such an assembly is also disclosed comprising the steps of:attaching optical cables to spigots;passing optical fibres through a bore in each spigot;retracting a sleeve over one spigot;splicing together the optical fibres;returning the sleeve over the spigots;tensioning the spliced optical fibers; and then, fixing the sleeve to both spigots.

Abstract: A converter of the flash type includes means for amplifying and d.c. level shifting portions of the input analog waveform fed to each A to D converter unit to provide each converter unit with a full voltage input swing relative to the reference voltage for conversion, thereby producing a more accurate digital output.

Abstract: To facilitate installation of cables through bulkheads and other surfaces and to provide electrical protection to apparatus connected to such cables, an assembly comprising electrically conductive blocks (6) clamped in a frame (2) is provided. The mounting blocks 6, each formed of two parts for fitting round a continuous cable length include ribs (11) adapted to grip the sleeving of the cable and an extended rib (10) for contacting screening of the cable. In use, the frame (2) is welded to a bulkhead or other conductive (earthed) element. A section of insulation is removed from the cable and on clamping of the assembly the blocks (6) are compressed together forcing ribs 10 to contact respective screens. Thus any induced electro-magnetic pulses on the cable screens are provided with a low-resistance leakage path.

Abstract: An integrated circuit having a built-in self test facility, the integrated circuit being partitioned into a number of sub-circuits each of which comprises a combinatorial logic circuit and a register. The sub-circuits are coupled together so that each combinatorial logic circuit has its inputs coupled to at least one register, has its outputs coupled to at least one register, and the output of the overall integrated circuit is taken from one or more registers. Each register has its fucntional mode controlled by predetermined signals to an associated local decoder, the functional modes of the registers being selected to initiate a test operation for the testing of the integrated circuit.

Abstract: A circuit (FIG. 4) in which a sub-circuit comprised of a bias transistor (T1), a feedback reisistor (R2) connected between the collector of this transistor (T1) and its base, and, a drive transistor (T2), is connected to its polarity-inverse sub-circuit (T1', R2', T2') in a ring configuration and is initiated by means of current injection from a start-up bias circuit. The latter may comprise a bias transistor (T1"), a drive transistor (T2") the base of which is connected to the collector of the bias transistor (T1"), and a pair of feedback current/voltage divider resistors (R1", R2") in the collector path of the bias transistor (T1"). Following start-up, constant current is maintained by feedback in the ring, and this current may be tapped at an appropriate point in the ring.

Abstract: A device which includes an arithmetic logic unit and a data shifter--e.f. a barrel shifter. The outputs of these are cross-coupled to their inputs by separate feedback connections. A third feedback connection is provided between the output of the arithmetic logic unit and another of its inputs. For added versatility in operation, registers at the output of the arithmetic logic unit and the barrel shifter may include each a selectable by-pass and/or additional registers may be included in parallel therewith. The device is reconfigured by the control of input multiplexers interposed between the feedback connections and the arithmetic logic unit and the barrel shifter.

Abstract: A fractional N synthesizer comprising a voltage controlled oscillator for producing an output signal which is afforded to a phase detector via a variable divider to provide a control signal for the voltage controlled oscillator in the presence of a phase difference between a reference signal from a reference source and the signal afforded thereto from the variable divider wherein the synthesizer is provided with first and second accumulators, the arrangement of the accumulators being such that an output signal from the arrangement is provided in which the interpolation sidebands of the first accumulator caused by quantization errors in the first accumulator are cancelled, means being provided for setting the division ratio of the variable divider in dependence upon the output signal.

Abstract: In a time division multiplexed digital switching system intercommunication between telephony groups is by way of a serially operated data bus (2). Allocation of bandwidth on the data bus (2) is on a needs basis under control of a common control responsive (3) to requests from either applications processors or interface modules (10,20). The interface modules (10,20) receive addressing information from the common control (5) on a serially operated control bus (1) only when a change of status of a communication at least partly affecting that module (10,20) occurs. Such changes of status include new communication set-ups, communication clear-down, bandwidth increase and bandwidth decrease. Dynamic re-allocation of bandwidth of the data bus (2) occurs without affecting communications in progress.

Abstract: A digital adaptive echo canceller for use in cancelling echo signals caused by trans-hybrid losses in two-wire to four-wire converters comprises first and second adaptive filters (20,22) each arranged to generate synthetic echo signals. Transfer control logic (23) compares difference signals relative to the difference between the synthetic echo signal generated by the first filter (22), and a real echo signal and the synthetic echo signal generated by the second filter (20) and the real echo signal, and if the synthetic echo signal from the first filter (22) is closer to the real echo signal causes transfer of the coefficients of the first filter (22) to the second filter (20) such that the synthetic signal mixed with transmitted speech signals in a mixer (24) is updated when necessary.

Abstract: The microprocessor interface device is for use in a telecomminications system including a microprocessor. The device includes a first interfacing means which receives signals from, and dispatches signals to, the telecommunications system. A second interfacing means receives signals from, and despatches signals to, the microprocessor. A memory is provided, together with arbitration means arranged to control the first and second interfacing means so that only one interfacing means at a time has access to the memory. Decoding means is adapted to respond to address signals presented to the second interfacing means by the microprocessor, to generate signals enabling areas of the telecommunications system to be accessed.

Abstract: The electronic component includes a mounting substrate having a surface provided with a plurality of spaced contact pads. A semiconductor chip is mounted on the substrate and includes at least one active element in the form of a photodiode on a substrate of light transmissive material. The active element has a metallized contact region and the semiconductor chip has a plurality of projecting metallized contact regions which are each electrically conductively bonded to a different one of the spaced contact pads of the mounting substrate. The photodiode may be a PIN diode and the semiconductor chips may be an integrated circuit to which the PIN diode is connected thereby providing an optical receiver equivalent to a PIN receiver.

Abstract: The invention concerns call-charge payment of telephone calls from payphone telephone instruments (PI) using a credit card, or the like. The invention provides credit transaction arrangements for automatic call-charge payment of calls established through a telecommunications network from payphone instruments (PI). The payphone (PI) is provided with a credit card reader (CRM) which when activated causes the payphone (PI) to automatically set-up a path (NAP) through the telecommunications network to credit transaction equipment (CCE) at a remote location (NP) within the network. Initially, a first record data (HEAD), being relevant to prior call-charge payment, is transmitted over the path (NAP), validated and stored (CDS) at the credit transaction equipment (CCE), and the path is promptly disconnected. The subscriber then sets-up a communication path through the network to a desired called subscriber for communication purposes.

Abstract: A method of aligning an optical fibre with a light source, such as a solid state laser, comprises substantially aligning the axis of optical fibre with the light source and locating two lenses between the fibre and the source. One of the lenses is fixed and the other is movable in a plane perpendicular to the axis of the fibre. The lens is moved until the image of the light source is focussed on to the end of the fibre, the fibre also being axially movable. The method can be termed an "optical lever", movement of the lens causing a smaller movement of the image. The requirement for fixing the fibre or the lens extremely accurately is therefore reduced.

Abstract: Apparatus for obtaining programmable threshold extension of an FM demodulator comprises a limiter preamplifier 4 and a variable gain buffer amplifier 6. The buffer amplifier 6 is provided with an external control node 16 such that the signal level fed from the buffer amplifier 6 to an injection locked oscillator/divider 8 can be programmed in dependence upon a control signal applied to the external control node 16. In this manner threshold extension of the FM demodulator can be selectively applied in dependence upon the noise level in an FM input signal to be demodulated. The limiter preamplifier 4 and the buffer amplifier 6 may form part of an automatic gain control circuit.

Abstract: A circuit arrangement for use in an integrated circuit having a built-in self test design, the circuit arrangement comprising first and second gates coupled to a flip-flop via a third gate. The present invention provides a multiplexer coupled to one input of the first gate, the multiplexer being controllable by a control signal to feed either input data or output data of the circuit arrangement to said one input of the first gate and a fourth gate coupled to an input of the second gate, the fourth gate having an input connected to receive a signal dependent on the control signal to the data selector means.

Abstract: The subscriber line signalling device (D) is employed in a digital telecommunications system. In particular the device (D) is used in a subscriber line interface module and it allows all signalling data to be detected and generated on a per-channel basis. A microprocessor (A) controls the device which generates and detects cyclically permutable code words on a plurality of traffic channel paths to or from the device. It is arranged that each generated cyclically permutable code word on any one traffic channel path is synchronously coded with respect to any other traffic channel path. The device can also be programmed to handle different data rates. In addition the operational modes of the traffic channels can be controlled giving loopback facilities allowing cyclically permutable code words to be generated and detected from the input and output traffic channels as desired and allow a diagnostic facility to be implemented.

Abstract: A high resolution analog to digital converter comprising a low resolution analog to digital converter and an interpolating digital to analog converter, the interpolating digital to analog converter having a second order digital controller and a one bit quantiser arranged in a feedback loop. The low resolution analog to digital converter is coupled to a multi-stage decimation filter having an algorithm of any stage thereof determined in dependence upon the algorithm of the immediately preceding stage.

Abstract: A method of selectively displaying data, whereby the data is arranged in a consecutive series of data-blocks, each data-block being a matrix of information such as a Lofargram. The method comprises selecting an initial set of data-blocks from the series of data-blocks, wherein the initial set of data-blocks comprises an initial data-block and every following nth data-block in the series and then displaying this initial set. The method includes displaying different sets of data-blocks subsequent to the initial set. Each different set of data-blocks comprises an initial data-block, differing from the initial data-block of the preceeding set by an integer m, and every subsequent nth data-block in the series. The method further comprises, displaying a reference data-block adjacent to any one of the sets of data-blocks for comparing with any one of the data-blocks in the series.

Abstract: A prior art method of depositing Germanium Carbide involves the use of glow discharge techniques which are problematic in that they require high substrate temperatures. Methods embodying the present invention comprise exposing a target of germanium to a plasma comprising an inert gas and a halocarbon gas. The plasma is maintained by means of a radio frequency magnetron electrode which is associated with the target. Atoms and ions of Germanium and Carbon are sputtered onto the substrate in order to deposit the Germanium Carbide.

Abstract: A power control system for the remote control of one or more remote power supply circuits in which a power controller which comprises means for producing an a.c. control signal which is arranged to be transmitted over a single pair of control conductors forming a part of a d.c. isolated control link to remote power supply circuit for the operation thereof, in which variable impedance switching means at the remote power supply circuit modifies the impedance reflected back over the control link to the power controller in accordance with the condition of the power supply switching circuit and in which detector means in the power controller senses changes in the impedance of the variable impedance switching circuit and accordingly provides an indication of the state of the remote power supply circuit.