Patents Assigned to Powerchip Semiconductor Corp.
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Publication number: 20120068147Abstract: A method for forming a phase change memory device is disclosed. A substrate with a bottom electrode thereon is provided. A heating electrode and a dielectric layer are formed on the bottom electrode, wherein the heating electrode is surrounded by the dielectric layer. The heating electrode is etched to form recess in the dielectric layer. A phase change material is deposited on the dielectric layer, filling into the recess. The phase change material is polished to remove a portion of the phase change material exceeding the surface of the dielectric layer and a phase change layer is formed confined in the recess of the dielectric layer. A top electrode is formed on the phase change layer and the dielectric layer.Type: ApplicationFiled: November 23, 2011Publication date: March 22, 2012Applicant: POWERCHIP SEMICONDUCTOR CORP.Inventors: Jen-Chi CHUANG, Ming-Jeng HUANG, Chien-Min LEE, Jia-Yo LIN, Min-Chih WANG
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Publication number: 20110312150Abstract: A phase change memory device is provided, including a substrate, a first dielectric layer disposed over the substrate, a first electrode disposed in the first dielectric layer, a second dielectric layer formed over the first dielectric layer, covering the first electrode, a heating electrode disposed in the second dielectric layer, contacting the first electrode, a phase change material layer disposed over the second dielectric layer, contacting the heating electrode, and a second electrode disposed over the phase change material layer. In one embodiment, the heating electrode includes a first portion contacting the first electrode and a second portion contacting the phase change material layer, and the second portion of the heating electrode includes metal silicides and the first portion of the heating electrode includes no metal silicides.Type: ApplicationFiled: August 26, 2011Publication date: December 22, 2011Applicant: POWERCHIP SEMICONDUCTOR CORP.Inventors: Chien-Min Lee, Ming-Jeng Huang, Jen-Chi Chuang, Jia-Yo Lin, Min-Chih Wang
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Patent number: 7951668Abstract: A process for fabricating crown capacitors is described. A substrate having a template layer thereon is provided. A patterned support layer is formed over the template layer. A sacrifice layer is formed over the substrate covering the patterned support layer. Holes are formed through the sacrifice layer, the patterned support layer and the template layer, wherein the patterned support layer is located at a depth at which bowing of the sidewalls of the holes occurs and is bowed less than the sacrifice layer at the sidewalls. A substantially conformal conductive layer is formed over the substrate. The conductive layer is then divided into lower electrodes of the crown capacitors.Type: GrantFiled: January 14, 2009Date of Patent: May 31, 2011Assignee: Powerchip Semiconductor Corp.Inventors: Kun-Jung Wu, Nagai Yukihiro
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Patent number: 7915660Abstract: A junction-free NAND flash memory is described, including a substrate, memory cells, source/drain inducing (SDI) gates electrically connected with each other, and a dielectric material layer. The memory cells are disposed on the substrate, wherein each memory cell includes a charge storage layer. Each SDI gate is disposed between two neighboring memory cells. The dielectric material layer is disposed between the memory cells and the SDI gates and between the SDI gates and the substrate.Type: GrantFiled: May 19, 2009Date of Patent: March 29, 2011Assignee: Powerchip Semiconductor Corp.Inventors: Houng-Chi Wei, Shi-Hsien Chen, Hsin-Heng Wang, Shih-Hsiang Lin
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Patent number: 7903470Abstract: An integrated circuit is provided. The integrated circuit includes a memory device and a discharge circuit. The discharge circuit discharges the well voltage line and the first voltage line of the memory device after the end of the erasing period and includes a first and second switch circuit and a first and second control voltage supplier. The first switch circuit is coupled between the well voltage line, the first voltage line and a second supplier. The second switch circuit is coupled between the first switch circuit and a reference voltage. The first control voltage supplier is coupled to the first switch circuit and supplies a first control voltage to turn on the first switch circuit during a first discharge period. The second control voltage supplier is coupled to the second switch circuit, and supplies a second control voltage to turn on the second switch circuit during a second discharge period.Type: GrantFiled: December 15, 2008Date of Patent: March 8, 2011Assignee: Powerchip Semiconductor Corp.Inventors: Te-Chang Tseng, Chun-Yi Tu, Hideki Arakawa, Yamasaki Kyoji
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Publication number: 20110053333Abstract: Phase change memory devices and methods for manufacturing the same are provided. An exemplary embodiment of a phase change memory device includes a bottom electrode formed over a substrate. A first dielectric layer is formed over the bottom electrode. A heating electrode is formed in the first dielectric layer and partially protrudes over the first dielectric layer, wherein the heating electrode includes an intrinsic portion embedded within the first dielectric layer, a reduced portion stacked over the intrinsic portion, and an oxide spacer surrounding a sidewall of the reduced portion. A phase change material layer is formed over the first dielectric layer and covers the heating electrode, the phase change material layer contacts a top surface of the reduced portion of the heating electrode. A top electrode is formed over the phase change material layer and contacts the phase change material layer.Type: ApplicationFiled: November 5, 2010Publication date: March 3, 2011Applicant: POWERCHIP SEMICONDUCTOR CORP.Inventors: Yung-Fa Lin, Te-Chun Wang
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Patent number: 7875982Abstract: A semiconductor device includes: an interlayer insulation film; a lower interconnection layer; an upper interconnection layer; and a via hole extending through the interlayer insulation film to establish electric connection between the lower and upper interconnections; wherein a plurality of interconnection lines is provided in the lower interconnection layer, and a contact region is formed for contact with the via hole by partially joining at least two interconnection lines, and a void exists in a first region of the interlayer insulation film located between adjacent interconnection lines, and no void exists in a second region of the interlayer insulation film located between a contacting portion of the via hole in the contact region and an interconnection line adjacent to the contact region, whereby reliably preventing any contact between a via hole and a void formed in an interlayer insulation film even when the via hole is greatly displaced.Type: GrantFiled: August 8, 2008Date of Patent: January 25, 2011Assignees: Renesas Electronics Corporation, Powerchip Semiconductor Corp.Inventor: Satoshi Abe
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Publication number: 20100295117Abstract: A junction-free NAND flash memory is described, including a substrate, memory cells, source/drain inducing (SDI) gates electrically connected with each other, and a dielectric material layer. The memory cells are disposed on the substrate, wherein each memory cell includes a charge storage layer. Each SDI gate is disposed between two neighboring memory cells. The dielectric material layer is disposed between the memory cells and the SDI gates and between the SDI gates and the substrate.Type: ApplicationFiled: May 19, 2009Publication date: November 25, 2010Applicant: POWERCHIP SEMICONDUCTOR CORP.Inventors: Houng-Chi Wei, Shi-Hsien Chen, Hsin-Heng Wang, Shih-Hsiang Lin
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Publication number: 20100252875Abstract: A structure of a non-volatile memory is described, including a substrate, isolation structures disposed in and protrudent over the substrate, floating gates as conductive spacers on the sidewalls of the isolation structures protrudent over the substrate, and a tunneling layer between each floating gate and the substrate. A process for fabricating a non-volatile memory is also described. Isolation structures are formed in a substrate protrudent over the same, a tunneling layer is formed over the substrate, and then floating gates are formed as conductive spacers on the sidewalls of the first isolation structures protrudent over the substrate.Type: ApplicationFiled: April 3, 2009Publication date: October 7, 2010Applicant: POWERCHIP SEMICONDUCTOR CORP.Inventor: Riichiro Shirota
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Patent number: 7803692Abstract: A method of manufacturing semiconductor devices having self-aligned contacts is provided. Multiple isolation structures are formed on the substrate to define an active area. Multiple gate structures are formed on the substrate. Multiple doped areas are formed in the substrate beside each gate structure. Multiple first spacers are formed on the sidewalls of each of the gate structure. Multiple second spacers are formed on the sidewalls of each of the isolation structure. A dielectric layer is formed on the substrate. Then, a self-aligned process is performed to form multiple contact openings in the dielectric layer between the gate structures. The conductive material is filled in the contact openings.Type: GrantFiled: September 18, 2009Date of Patent: September 28, 2010Assignee: Powerchip Semiconductor Corp.Inventors: Min-San Huang, Hann-Jye Hsu, Yung-Chung Yao
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Publication number: 20100213432Abstract: A method for forming a phase change memory device is disclosed. A substrate with a bottom electrode thereon is provided. A heating electrode and a dielectric layer are formed on the bottom electrode, wherein the heating electrode is surrounded by the dielectric layer. The heating electrode is etched to form recess in the dielectric layer. A phase change material is deposited on the dielectric layer, filling into the recess. The phase change material is polished to remove a portion of the phase change material exceeding the surface of the dielectric layer and a phase change layer is formed confined in the recess of the dielectric layer. A top electrode is formed on the phase change layer and the dielectric layer.Type: ApplicationFiled: May 19, 2009Publication date: August 26, 2010Applicants: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE, POWERCHIP SEMICONDUCTOR CORP., NANYA TECHNOLOGY CORPORATION, PROMOS TECHNOLOGIES INC., WINBOND ELECTRONICS CORP.Inventors: Jen-Chi Chuang, Ming-Jeng Huang, Chien-Min Lee, Jia-Yo Lin, Min-Chih Wang
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Patent number: 7778087Abstract: A memory programming method is provided. A first programming operation is performed to program a multi level cell from an initial state to a first target state, which corresponds to a storage data and has a first threshold voltage range. A flag bit of the NAND flash is set to a first state to indicate that the first programming operation has been performed. A second programming operation is performed to program the multi level cell from the first target state to a second target state, which corresponds to the storage data and has a second threshold voltage range. The flag bit is set to a second state to indicate that the second programming operation has been performed.Type: GrantFiled: December 16, 2008Date of Patent: August 17, 2010Assignee: Powerchip Semiconductor Corp.Inventors: Chun-Yi Tu, Te-Chang Tseng, Hideki Arakawa, Takeshi Nakayama
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Publication number: 20100177459Abstract: A process for fabricating crown capacitors is described. A substrate having a template layer thereon is provided. A patterned support layer is formed over the template layer. A sacrifice layer is formed over the substrate covering the patterned support layer. Holes are formed through the sacrifice layer, the patterned support layer and the template layer, wherein the patterned support layer is located at a depth at which bowing of the sidewalls of the holes occurs and is bowed less than the sacrifice layer at the sidewalls. A substantially conformal conductive layer is formed over the substrate. The conductive layer is then divided into lower electrodes of the crown capacitors.Type: ApplicationFiled: January 14, 2009Publication date: July 15, 2010Applicant: Powerchip Semiconductor Corp.Inventors: Kun-Jung Wu, Nagai Yukihiro
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Publication number: 20100172181Abstract: Within a page buffer 14 which is coupled to a non-volatile memory cell array 10 and temporally stores data as the data with a predetermined page unit is written in and read out to/from the memory cell array 10, at least one latch circuit 14v-1 including a bit line selector 14s, a page buffer unit circuit 14u including two latch L1, L2, and a latch L3 is set up for a plurality of bit lines. The bit line selector 14s selects one bit line and couples it to the page buffer unit circuit 14u. The latch L1 temporally stores the data which are read out from the memory cell of the selected bit line, and then outputs the data through the latch L2 or L3. On the other hand, the latch L1 temporally stores the programming data inputted through the latch L2 or L3, and after that outputs it to the memory cell of the selected bit line for programming.Type: ApplicationFiled: November 6, 2009Publication date: July 8, 2010Applicant: POWERCHIP SEMICONDUCTOR CORP.Inventor: Hiroki Murakami
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Publication number: 20100163828Abstract: A phase change memory device is provided, including a semiconductor substrate with a first conductive semiconductor layer disposed thereover, wherein the first conductive semiconductor layer has a first conductivity type. A first dielectric layer is disposed over the semiconductor substrate. A second conductive semiconductor layer having a second conductivity type opposite to the first conductivity type is disposed in the first dielectric layer. A heating electrode is disposed in the first dielectric layer and formed over the second conductive semiconductor layer, wherein the heating electrode has a tapered cross section and includes metal silicide. A second dielectric layer is disposed over the first dielectric layer. A phase change material layer is disposed in the second dielectric layer. An electrode is disposed over the second dielectric layer, covering the phase change material layer.Type: ApplicationFiled: May 11, 2009Publication date: July 1, 2010Applicants: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE, POWERCHIP SEMICONDUCTOR CORP., NANYA TECHNOLOGY CORPORATION, PROMOS TECHNOLOGIES INC., WINBOND ELECTRONICS CORP.Inventor: Li-Shu Tu
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Publication number: 20100165720Abstract: A verification circuit for a phase change memory array is provided. A sensing unit senses a sensing voltage from a memory cell of the phase change memory array according to an enable signal. A comparator generates a comparing signal according to the sensing voltage and a reference voltage, so as to indicate whether the memory cell is in a reset state. A control unit generates a control signal according to the enable signal. An operating unit generates a first signal according to the control signal, so as to indicate whether the comparator is active.Type: ApplicationFiled: June 16, 2009Publication date: July 1, 2010Applicants: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE, POWERCHIP SEMICONDUCTOR CORP., NANYA TECHNOLOGY CORPORATION, PROMOS TECHNOLOGIES INC., WINBOND ELECTRIC CORP.Inventors: Wen-Pin Lin, Shyh-Shyuan Sheu, Pei-Chia Chiang
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Publication number: 20100133495Abstract: A phase change memory device is provided, including a substrate, a first dielectric layer disposed over the substrate, a first electrode disposed in the first dielectric layer, a second dielectric layer formed over the first dielectric layer, covering the first electrode, a heating electrode disposed in the second dielectric layer, contacting the first electrode, a phase change material layer disposed over the second dielectric layer, contacting the heating electrode, and a second electrode disposed over the phase change material layer. In one embodiment, the heating electrode includes a first portion contacting the first electrode and a second portion contacting the phase change material layer, and the second portion of the heating electrode includes metal silicides and the first portion of the heating electrode includes no metal silicides.Type: ApplicationFiled: September 2, 2009Publication date: June 3, 2010Applicant: POWERCHIP SEMICONDUCTOR CORP.Inventors: Chien-Min Lee, Ming-Jeng Huang, Jen-Chi Chuang, Jia-Yo Lin, Min-Chih Wang
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Publication number: 20100117050Abstract: A phase-change memory element with an electrically isolated conductor is provided. The phase-change memory element includes: a first electrode and a second electrode; a phase-change material layer electrically connected to the first electrode and the second electrode; and at least two electrically isolated conductors, disposed between the first electrode and the second electrode, directly contacting the phase-change material layers.Type: ApplicationFiled: November 12, 2008Publication date: May 13, 2010Applicants: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE, POWERCHIP SEMICONDUCTOR CORP., NANYA TECHNOLOGY CORPORATION, PROMOS TECHNOLOGIES INC., WINBOND ELECTRONICS CORP.Inventors: Frederick T. Chen, Ming-Jinn Tsai
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Publication number: 20100093142Abstract: A method of fabricating a device is described. A substrate having at least two isolation structures is provided. A first oxide layer and a first conductive layer are sequentially formed on the substrate between the isolation structures. A first nitridation process is performed to form a first nitride layer on the surface of the first conductive layer and a first oxynitride layer on the surface of the isolation structures. A second oxide layer is formed on the first nitride layer and first oxynitride layer. A densification process is performed to oxidize the first oxynitride layer on the surface of the isolation structures. A second nitride layer and a third oxide layer are sequentially formed on the second oxide layer. A second nitridation process is performed to form a third nitride layer on the surface of the third oxide layer. A second conductive layer is formed on the third nitride layer.Type: ApplicationFiled: October 9, 2008Publication date: April 15, 2010Applicant: POWERCHIP SEMICONDUCTOR CORP.Inventors: Ching-Yuan Ho, Hirotake Fujita, Po-Jui Chiang
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Publication number: 20100081273Abstract: A method for fabricating a conductive pattern including following steps is provided. A first conductive layer is formed on a substrate. A patterned hard mask layer is formed on the first conductive layer. A portion of the first conductive layer is removed to expose a portion of the substrate by using the patterned hard mask layer as a mask. A dielectric layer covering the patterned hard mask layer is formed on the substrate. A portion of the dielectric layer is removed to expose the patterned hard mask layer. The patterned hard mask layer is removed to form an opening in the dielectric layer. A second conductive layer is formed in the opening.Type: ApplicationFiled: September 30, 2008Publication date: April 1, 2010Applicant: POWERCHIP SEMICONDUCTOR CORP.Inventors: Jung-Yuan Hsieh, Yung-Ching Chen