Abstract: An image sensor package includes an image sensor chip having a chip body, a metal dam, and a transparent substrate having a surface. The chip body has an active surface including a photosensitive area and a non-sensitive area surrounding the photosensitive area. The metal dam is formed on the non-sensitive area of the active surface, surrounds a photosensitive layer formed on the photosensitive area at intervals, is electrically insulated from the chip body, and has a thickness. A glue dam is formed on the surface and is aligned with and is bonded to the metal dam. A thickness of the glue dam is less than the thickness of the metal dam. Accordingly, the metal dam and the glue dam are combined to form a dam structure, and the quantity of liquid glue to form the glue dam is decreased. Thus, the yield of the image sensor package is enhanced.

Abstract: A fan-out semiconductor package includes: a redistribution structure; a functional chip coupled to the redistribution structure; an isolation structure disposed on the redistribution structure and including a body formed with through-holes; a shielding structure disposed on the isolation structure and the redistribution structure; a first conductive pattern structure disposed on the isolation structure and extending through the through-holes of the isolation structure; an encapsulating structure disposed on the isolation structure, the shielding structure and the first conductive pattern structure; and a second conductive pattern structure disposed on the encapsulating structure. A method for manufacturing the fan-out semiconductor package is also disclosed.

Abstract: A package structure including a chip, an encapsulant, a first redistribution circuit structure, a second redistribution circuit structure, a conductive member, and a coded structure is provided. The encapsulant has a first encapsulating surface and a second encapsulating surface opposite thereto. The encapsulant covers the chip. The first redistribution circuit structure is disposed on the first encapsulating surface of the encapsulant. The second redistribution circuit structure is disposed on the second encapsulating surface of the encapsulant. The chip is electrically connected to the first redistribution circuit structure or the second redistribution circuit structure. The conductive member penetrates through the encapsulant to be electrically connected to the first redistribution circuit structure and the second redistribution circuit structure. The coded structure is disposed on the second redistribution circuit structure. The coded structure includes a readable coded pattern.

Abstract: A package structure and a manufacturing method thereof are provided. The package structure includes a redistributed circuit structure, a plurality of chips, a second encapsulant, a plurality of supporting members, a first encapsulant, and a plurality of connection terminals is provided. The redistributed circuit structure has a first surface and a second surface opposite to each other. The chips are disposed on the second surface of the redistributed circuit structure. The second encapsulant is disposed on the second surface of the redistributed circuit structure and covers the chips. The supporting members are disposed on the first surface of the redistributed circuit structure. The first encapsulant is disposed on the first surface of the redistributed circuit structure and covers the supporting members. The connection terminals are connected to the supporting members.

Abstract: A package structure including a redistributed circuit structure, a plurality of chips, a second encapsulant, a plurality of supporting members, a first encapsulant, and a plurality of connection terminals are provided. The redistributed circuit structure has a first surface and a second surface opposite thereto. The chips are disposed on the second surface of the redistributed circuit structure. The second encapsulant is disposed on the second surface of the redistributed circuit structure and covers the chips. The supporting members are disposed on the first surface of the redistributed circuit structure. The first encapsulant is disposed on the first surface of the redistributed circuit structure and covers the supporting members. The connection terminals are connected to the supporting members.

Abstract: A package structure including a first redistribution circuit structure, a chip, a second redistribution circuit structure, a plurality of packages, and a plurality of limiting connectors is provided. The chip is disposed on the first redistribution circuit structure. The second redistribution circuit structure is disposed on the chip. The plurality of packages are disposed on the second redistribution circuit structure. Each of the packages includes an encapsulant. The plurality of limiting connectors are disposed between each of the packages and the second redistribution circuit structure.

Abstract: A chip-middle type fan-out panel-level package (FOPLP) has a routing layer, a polyimide layer formed on the routing layer and having a plurality of pillar openings and a chip opening, a plurality of metal pillars mounted on the routing layer through the corresponding pillar openings, a chip mounted on the first routing layer through the chip opening and a molding compound formed on the polyimide layer to encapsulate the metal pillars and the chip. The polyimide layer is used to control the warpage of the FOPLP. The polyimide layer is formed inside the FOPLP and the chip is directly mounted on the first routing layer through the chip opening, so a height of the FOPLP is not increased when the first PI layer is added.

Abstract: A package structure includes a chip and a dielectric. The chip includes a chip connector disposed on an active surface of the chip. The dielectric is at least disposed on the active surface of the chip. The chip connector has a top surface and a side surface connected to the top surface. The dielectric does not directly cover part of the side surface close to the top surface.

Abstract: A package structure including a first die, a second die, an encapsulant, a dam structure, a light-transmitting sheet, a conductive connector, a circuit layer, and a conductive terminal is provided. The first die includes a first active surface. The first active surface has a sensing area. The second die is arranged such that a second back surface thereof faces the first die. The encapsulant covers the second die. The encapsulant has a first encapsulating surface and a second encapsulating surface. The dam structure is located on the first encapsulating surface and exposes the sensing area. The light-transmitting sheet is located on the dam structure. The conductive connector penetrates the encapsulant. The circuit layer is located on the second encapsulating surface. The first die is electrically connected to the second die through the conductive connector and the circuit layer. The conductive terminal is disposed on the circuit layer.

Abstract: An image sensor includes a chip, a cover, a first dam layer, and a second dam layer. The chip has a sensing area. The cover covers the chip. The first dam layer and the second dam layer are located between the chip and the cover and surround the sensing area. The second dam layer is located between the first dam layer and the chip, and a width of the first dam layer is greater than a width of the second dam layer, and the first dam layer is extended to the sensing area by a distance. A manufacturing method of an image sensor is also provided.

Abstract: A package structure including a first die, a second die, a dielectric body, a conductive terminal, a circuit layer and a patterned insulating layer is provided. The second die is disposed on the first die. A second active surface of the second die faces a first active surface of the first die. The dielectric body covers the first die. The conductive terminal is disposed on the dielectric body and opposite to the second die. The circuit layer includes a first circuit portion and a second circuit portion. The first circuit portion penetrates the dielectric body. The first die is electrically connected to the conductive terminal through the first circuit portion. The second circuit portion is embedded in the dielectric body. The second die is electrically connected to the first die through the second circuit portion. The patterned insulating layer covers the circuit layer and is embedded in the dielectric body.

Abstract: A packaging structure including first, second, and third dies, an encapsulant, a circuit structure, and a filler is provided. The encapsulant covers the first die. The circuit structure is disposed on the encapsulant. The second die is disposed on the circuit structure and is electrically connected to the circuit structure. The third die is disposed on the circuit structure and is electrically connected to the circuit structure. The third die has an optical signal transmission area. The filler is disposed between the second die and the circuit structure and between the third die and the circuit structure. A groove is present on an upper surface of the circuit structure. The upper surface includes first and second areas located on opposite sides of the groove. The filler directly contacts the first area. The filler is away from the second area. A manufacturing method of a packaging structure is also provided.

Abstract: A chip structure has a chip body having a plurality of pads, a plurality of metal bumps respectively formed on the pads, and a patterned bump directly formed on the chip body. The patterned bump has at least two different upper and lower plane patterns. A top surface of each of the metal bumps is higher than a height position on which the upper plane pattern is. When the chip structure is ground to the height position, the ground tops of the metal bumps and the upper plane pattern are flush. Therefore, detecting whether the upper plane pattern is exposed determines whether all the metal bumps are exposed and flush to each other to avoid insufficient grinding depth or over-ground.

Abstract: An image sensor package with low light-sensing noise has a chip body having a photosensitive area and non-sensitive area. The photosensitive area includes a photosensitive layer having a plurality of photosensitive units. A color filter is disposed on the photosensitive layer and has a plurality of filter units corresponding to the photosensitive units and a black matrix. A black adhesive layer is disposed on the non-sensitive area for mounting a glass cover. A gap is kept between the glass cover and the first surface of the chip body. When an incident light passes through the glass cover and emits to the photosensitive area, the black matrix absorbs the light traveling through the filter unit toward the photosensitive units adjacent to the filter unit. Furthermore, a light emitting to the non-sensitive area can be absorbed by the black adhesive layer. Thus, a light-sensing noise of the chip can be effectively decreased.

Abstract: A fan-out package structure of an image sensing device includes an image sensing unit having an image sensor with opposite sensing surface and connecting surface, a spacer layer surrounding a central portion of the sensing surface, and a light-transmitting cover plate disposed on the spacer layer spaced apart from and covering the sensing surface. An image signal processor is disposed on the connecting surface. A redistribution layer covers the image signal processor and the connecting surface, and includes a fan-out area. An encapsulation layer is disposed on the fan-out area, surrounds and covers an outer periphery of the image sensing unit, and allows a top surface of the light-transmitting cover plate to be exposed. A method of manufacturing a fan-out package structure of an image sensing device is also disclosed.

Abstract: A package structure including a first die, an encapsulant, a first circuit structure, a second circuit structure, a conductive connector, a second die, and a filler is provided. The encapsulant covers the first die and has a first surface and a second surface opposite to each other. The first circuit structure is disposed on the first surface. The second circuit structure is disposed on the second surface. The conductive connector penetrates the encapsulant. The second die is disposed on the second circuit structure. The second die has an optical signal transmission area. The filler is disposed between the second die and the second circuit structure. An upper surface of the second circuit structure has a groove. The upper surface includes a first area and a second area disposed on opposite sides of the groove. The filler directly contacts the first area. The filler is disposed away from the second area.

Abstract: A semiconductor packaging assembly includes a redistribution layered structure having a plurality of device regions and a plurality of cutting regions separating the device regions, a plurality of recess structures respectively formed in the cutting regions, a plurality of chips respectively disposed in the device regions, and an encapsulating layer formed on the redistribution layered structure to fill the recess structures and enclose the chips.

Abstract: A semiconductor package has a substrate, a chip and an encapsulation. The substrate has a dielectric layer, a copper wiring layer and a solder resist layer formed thereon. The copper wiring layer is formed on the dielectric layer and is covered by the solder resist layer. The solder resist layer has a chip area defined thereon and an annular opening formed thereon. The annular opening surrounds the chip area and exposes part of the copper wiring layer. The chip is mounted on the chip area and is encapsulated by the encapsulation. Therefore, the semiconductor package with the annular opening makes the solder resist layer discontinuous, and the concentration stress is decreased to avoid a crack formed on the solder resist layer or the copper wiring layer when doing thermal-cycle test.

Abstract: A test head assembly for a semiconductor device has a carrier, a pin seat and a test wire assembly. The carrier is formed in an L shape and has a lateral board, a perpendicular board and a opening formed through the perpendicular board. The pin seat is mounted in the corresponding opening. The test wire assembly has a test head, a plurality of connectors and a plurality of test wires. The test head is mounted on an outer sidewall of the lateral board and connected to the pin seat through the test wires and the connectors. Therefore, the pin seat is mounted on the perpendicular board of the L-shaped uprightly and the test head is mounted on the lateral board. The pin seat and the test head are not parallel to each other, and a lateral size of the test head assembly is reduced to increase the space usage.

Abstract: A chip-middle type fan-out panel-level package (FOPLP) has a routing layer, a polyimide layer formed on the routing layer and having a plurality of pillar openings and a chip opening, a plurality of metal pillars mounted on the routing layer through the corresponding pillar openings, a chip mounted on the first routing layer through the chip opening and a molding compound formed on the polyimide layer to encapsulate the metal pillars and the chip. The polyimide layer is used to control the warpage of the FOPLP. The polyimide layer is formed inside the FOPLP and the chip is directly mounted on the first routing layer through the chip opening, so a height of the FOPLP is not increased when the first PI layer is added.