Abstract: A package structure and a manufacturing method thereof are provided. The package structure includes a first package including a first redistribution layer, at least one chip and a second redistribution layer, and at least one second package disposed on the first package and including a substrate, an adhesive layer, at least two optical chips, an encapsulant layer, and a third redistribution layer. The optical chips are attached to a surface of the substrate close to the first package through the adhesive layer, and each optical chip has an optical surface close to the substrate. The encapsulant layer is disposed on the surface and surrounds the optical chips. The third redistribution layer is disposed between the encapsulant layer and the second redistribution layer, in which the second redistribution layer is electrically connected to the optical chips through the third redistribution layer.

Abstract: A stacked package device has a first package and a second package vertically stacked and electrically connected to each other. One or each of the first package and the second package includes a first substrate, a second substrate and an intermediate substrate. A first flip-chip and a second flip-chip are respectively mounted on opposite surfaces of the first substrate and the second substrate. The intermediate substrate is electrically connected between the opposite surfaces of the first substrate and the second substrate for signal transmission between the first flip-chip and the second flip-chip. The use of the intermediate substrate avoids the structure damage resulting from thermal stress. Since no encapsulant is provided to cover each flip-chip, the problem of separation between the encapsulant and the substrates is avoided.

Abstract: A package structure includes a substrate, an interposer module, a chip module, and a first encapsulant. The interposer module is arranged on the substrate. The chip module is arranged on the interposer module. The chip module is electrically connected to the substrate through the interposer module. The first encapsulant encapsulates the chip module and the interposer module and directly contacts the substrate. A bottom surface of the first encapsulant and a top surface of the substrate are coplanar. A manufacturing method of a package structure is also disclosed.

Abstract: Provided is a package structure, which includes a substrate, an interposer module, and a chip module. The interposer module is disposed on the substrate. The interposer module includes a first insulating layer, a second insulating layer, and multiple dummy terminals. The first insulating layer is disposed between the second insulating layer and the substrate. The multiple dummy terminals are in direct contact with the first insulating layer and the substrate. The chip module is disposed on the interposer module and is electrically connected to the substrate through the interposer module. Also provided is a manufacturing method of a package structure. The plurality of external terminals include a plurality of functional components. The substrate is disposed between the plurality of dummy terminals and the plurality of external terminals, and the plurality of dummy terminals are electrically insulated the plurality of functional components.

Abstract: A package structure and a manufacturing method thereof are provided. The package structure includes a redistribution layer, a conductive pillar, an active chip, an encapsulation layer, and another redistribution layer. The conductive pillar and the active chip are side by side disposed on the redistribution layer. The encapsulation layer surrounds the active chip and the conductive pillar, in which the encapsulation layer has a first through hole disposed between the active chip and the redistribution layer and a second through hole disposed between the conductive pillar and the redistribution layer, and a depth of the first through hole is less than a depth of the second through hole. The another redistribution layer is disposed on a side of the redistribution layer away from the redistribution layer and electrically connected to the redistribution layer through the conductive pillar.

Abstract: A package device and a manufacturing method thereof are provided. The package device includes a substrate, a plurality of conductive pillars, a redistribution layer, at least one bridge chip, at least two active chips, an encapsulant, and an underfill layer. The conductive pillars are disposed on the substrate side by side, the redistribution layer is disposed on the conductive pillars, and the bridge chip is disposed between the substrate and the redistribution layer. The active chips are disposed on the redistribution layer, the bridge chip is coupled between the active chips, and the encapsulant is disposed on the redistribution layer and surrounds the active chips. The underfill layer is disposed between adjacent two of the conductive pillars and between one of the conductive pillars and the bridge chip.

Abstract: A semiconductor package structure includes a first package and a second package. The first package includes a first redistribution layer, a second redistribution layer, a third redistribution layer, at least one first chip, at least one second chip, multiple first conductive elements, multiple second conductive elements, a first encapsulant, a second encapsulant, and multiple solders. The second redistribution layer is located between the first redistribution layer and the third redistribution layer and includes multiple chip connectors. Each chip connector includes a connecting pad, a nickel layer, and a gold layer. The connecting pad has top surface and a peripheral surface. The nickel layer covers the top surface and the peripheral surface of the connecting pad, and the gold layer covers the nickel layer located on the top surface of the connecting pad. The second encapsulant is disposed on the third redistribution layer and is electrically connected to the first encapsulant.

Abstract: A semiconductor package component which has an outer profile including an oblique package edge obliquely interconnecting between two adjacent side walls. The semiconductor package component includes a first redistribution layer (RDL) unit, a chip unit, a dummy die unit, an encapsulation layer, and a second RDL unit. The chip unit is disposed on the first RDL unit. The dummy die unit includes a dummy die that is disposed on the first RDL unit, and has a dummy die edge which extends in a direction parallel to the oblique package edge. A method for making the semiconductor package component is also disclosed.

Abstract: An image sensor package includes an image sensor chip having a chip body, a metal dam, and a transparent substrate having a surface. The chip body has an active surface including a photosensitive area and a non-sensitive area surrounding the photosensitive area. The metal dam is formed on the non-sensitive area of the active surface, surrounds a photosensitive layer formed on the photosensitive area at intervals, is electrically insulated from the chip body, and has a thickness. A glue dam is formed on the surface and is aligned with and is bonded to the metal dam. A thickness of the glue dam is less than the thickness of the metal dam. Accordingly, the metal dam and the glue dam are combined to form a dam structure, and the quantity of liquid glue to form the glue dam is decreased. Thus, the yield of the image sensor package is enhanced.

Abstract: A semiconductor packaging assembly includes a redistribution layered structure having a plurality of device regions and a plurality of cutting regions separating the device regions, a plurality of recess structures respectively formed in the cutting regions, a plurality of chips respectively disposed in the device regions, and an encapsulating layer formed on the redistribution layered structure to fill the recess structures and enclose the chips.

Abstract: A low warpage chip includes a chip body, a plurality of signal contacts, and an anti-warpage layer. The chip body has a back surface and an active surface opposite to each other and has a circuit layer inside. The plurality of signal contacts are configured on the active surface and are electrically connected to the circuit layer. The anti-warpage layer covers at least a part of the back surface. A thermal expansion coefficient of the anti-warpage layer is greater than a thermal expansion coefficient of the chip body. When the low warpage chip undergoes a thermal processing procedure, the anti-warpage layer mitigates the warpage of the chip body to maintain the chip body in a relatively flat state.

Abstract: A package structure and a manufacturing method thereof are provided. The package structure includes a redistribution layer, a conductive element, an active chip, an encapsulation layer, another redistribution layer, and a conductive terminal. The conductive element, the active chip, and the encapsulation layer are disposed on the redistribution layer and the encapsulation layer surrounds the conductive element and the active chip. The another redistribution layer is disposed on the conductive element, the active chip and the encapsulation layer and electrically connected to the redistribution layer through the conductive element.

Abstract: A package device and a manufacturing method thereof are provided. The package device includes a package structure, a redistribution layer, an underfill layer, a plurality of conductive pillars, another redistribution layer, and an encapsulant. The underfill layer is disposed between the package structure and the redistribution layer, and the conductive pillars and the package structure are disposed side by side between the redistribution layers. The encapsulant is disposed between the redistribution layers and surrounds the package structure and the conductive pillars.

Abstract: A semiconductor package structure includes a redistribution structure layer, at least one chip, an encapsulant, and multiple solder balls. The redistribution structure layer includes multiple first connectors located on a first side. Each first connector includes a connecting pad, a soldering pad, and multiple conductive blind holes located between the connecting pad and the soldering pad. The conductive blind holes are disposed separately from each other and connect the connecting pad and the soldering pad. The chip is disposed on a second side of the redistribution structure layer and electrically connected to the redistribution structure layer. The encapsulant is disposed on the second side and at least covers the chip and the second side. The solder balls are disposed on the first side of the redistribution structure layer and electrically connected to the redistribution structure layer. The solder balls are respectively connected to the connecting pad of each first connector.

Abstract: An image sensor package with low light-sensing noise has a chip body having a photosensitive area and non-sensitive area. The photosensitive area includes a photosensitive layer having a plurality of photosensitive units. A color filter is disposed on the photosensitive layer and has a plurality of filter units corresponding to the photosensitive units and a black matrix. A black adhesive layer is disposed on the non-sensitive area for mounting a glass cover. A gap is kept between the glass cover and the first surface of the chip body. When an incident light passes through the glass cover and emits to the photosensitive area, the black matrix absorbs the light traveling through the filter unit toward the photosensitive units adjacent to the filter unit. Furthermore, a light emitting to the non-sensitive area can be absorbed by the black adhesive layer. Thus, a light-sensing noise of the chip can be effectively decreased.

Abstract: A chip structure has a chip body having a plurality of pads, a plurality of metal bumps respectively formed on the pads, and a patterned bump directly formed on the chip body. The patterned bump has at least two different upper and lower plane patterns. A top surface of each of the metal bumps is higher than a height position on which the upper plane pattern is. When the chip structure is ground to the height position, the ground tops of the metal bumps and the upper plane pattern are flush. Therefore, detecting whether the upper plane pattern is exposed determines whether all the metal bumps are exposed and flush to each other to avoid insufficient grinding depth or over-ground.

Abstract: A package structure including a first chip, a second chip, a plurality of fourth chips, a first redistribution layer, a second redistribution layer, a third redistribution layer, a first dielectric body, a second dielectric body, and a conductive member is provided. The first chip is disposed between the first redistribution layer and the third redistribution layer. The conductive member is disposed between the first redistribution layer and the second redistribution layer. The second redistribution layer is electrically connected to the first chip through the conductive member and the first redistribution layer. The second redistribution layer is disposed between the second chip and the fourth chip. Two of the fourth chips are electrically connected to each other through the second redistribution layer and the second chip.

Abstract: Disclosed is a packaging structure including a first chip, a second chip, multiple fourth chips, a first redistribution layer, a second redistribution layer, a third redistribution layer, a first dielectric body, a second dielectric body, and a conductive member. The first chip is disposed between the first redistribution layer and the third redistribution layer. The conductive member is disposed between the first redistribution layer and the second redistribution layer. The second redistribution layer is electrically connected to the first chip by the conductive member and the first redistribution layer, and is disposed between the second chip and the fourth chip. Two fourth chips are electrically connected to each other by the second redistribution layer and the second chip. The first dielectric body covers the second chip, the first redistribution layer, the second redistribution layer, and the conductive member. The second dielectric body covers the second redistribution layer.

Abstract: A three-dimensional (3D) semiconductor package component includes a carrier substrate, a first redistribution layer unit, at least one 3D packaging chip, an encapsulation layer and a second redistribution layer unit. The first redistribution layer unit is formed on a surface of the carrier substrate. The at least one 3D packaging chip is formed on the first redistribution layer unit. The encapsulation layer covers a surface of the first redistribution layer unit and encapsulates at least one 3D packaging chip. The second redistribution layer unit is formed on a surface of the encapsulation layer opposite to the first redistribution layer unit. A method for making the 3D semiconductor package component is also provided.

Abstract: A fan-out package structure of an image sensing device includes an image sensing unit having an image sensor with opposite sensing surface and connecting surface, a spacer layer surrounding a central portion of the sensing surface, and a light-transmitting cover plate disposed on the spacer layer spaced apart from and covering the sensing surface. An image signal processor is disposed on the connecting surface. A redistribution layer covers the image signal processor and the connecting surface, and includes a fan-out area. An encapsulation layer is disposed on the fan-out area, surrounds and covers an outer periphery of the image sensing unit, and allows a top surface of the light-transmitting cover plate to be exposed. A method of manufacturing a fan-out package structure of an image sensing device is also disclosed.