Abstract: A stacked package structure and a manufacturing method thereof are provided. The stacked package structure includes an upper redistribution layer, a first chip, and an upper molding layer. The first chip is disposed on the upper redistribution layer and is electrically connected to the upper redistribution layer. The upper molding layer is disposed on the first chip and the upper redistribution layer, and is configured to package the first chip. The upper molding layer includes a recess, the recess is recessed relative to a surface of the upper molding layer away from the upper redistribution layer, and the recess is circumferentially formed around a periphery of the upper molding layer.

Abstract: A packaging structure including first, second, and third dies, an encapsulant, a circuit structure, and a filler is provided. The encapsulant covers the first die. The circuit structure is disposed on the encapsulant. The second die is disposed on the circuit structure and is electrically connected to the circuit structure. The third die is disposed on the circuit structure and is electrically connected to the circuit structure. The third die has an optical signal transmission area. The filler is disposed between the second die and the circuit structure and between the third die and the circuit structure. A groove is present on an upper surface of the circuit structure. The upper surface includes first and second areas located on opposite sides of the groove. The filler directly contacts the first area. The filler is away from the second area. A manufacturing method of a packaging structure is also provided.

Abstract: A package structure and a manufacturing method thereof are provided. The package structure includes a redistribution layer, a conductive element, an active chip, an encapsulation layer, another redistribution layer, and a conductive terminal. The conductive element, the active chip, and the encapsulation layer are disposed on the redistribution layer and the encapsulation layer surrounds the conductive element and the active chip. The another redistribution layer is disposed on the conductive element, the active chip and the encapsulation layer and electrically connected to the redistribution layer through the conductive element.

Abstract: A package structure and a manufacturing method thereof are provided. The package structure includes a redistribution layer, a conductive pillar, an active chip, an encapsulation layer, and another redistribution layer. The conductive pillar and the active chip are side by side disposed on the redistribution layer. The encapsulation layer surrounds the active chip and the conductive pillar, in which the encapsulation layer has a first through hole disposed between the active chip and the redistribution layer and a second through hole disposed between the conductive pillar and the redistribution layer, and a depth of the first through hole is less than a depth of the second through hole. The another redistribution layer is disposed on a side of the redistribution layer away from the redistribution layer and electrically connected to the redistribution layer through the conductive pillar.

Abstract: An image sensor package with low light-sensing noise has a chip body having a photosensitive area and non-sensitive area. The photosensitive area includes a photosensitive layer having a plurality of photosensitive units. A color filter is disposed on the photosensitive layer and has a plurality of filter units corresponding to the photosensitive units and a black matrix. A black adhesive layer is disposed on the non-sensitive area for mounting a glass cover. A gap is kept between the glass cover and the first surface of the chip body. When an incident light passes through the glass cover and emits to the photosensitive area, the black matrix absorbs the light traveling through the filter unit toward the photosensitive units adjacent to the filter unit. Furthermore, a light emitting to the non-sensitive area can be absorbed by the black adhesive layer. Thus, a light-sensing noise of the chip can be effectively decreased.

Abstract: A package structure and a manufacturing method thereof are provided. The package structure includes a first package and a second package, and the second package is disposed on the first package. The first package includes a first redistribution layer, at least one chip and a second redistribution layer. The chip is disposed between the first redistribution layer and the second redistribution layer. The second package includes a third redistribution layer and at least three light-emitting elements. The third redistribution layer is electrically connected to the second redistribution layer, and the second redistribution layer is disposed between the chip and the third redistribution layer. The light-emitting elements are disposed on the third redistribution layer and electrically connected to the third redistribution layer. Each light-emitting element includes a first surface opposite to the third redistribution layer, and the first surfaces of the light-emitting elements are coplanar.

Abstract: A chip structure has a chip body having a plurality of pads, a plurality of metal bumps respectively formed on the pads, and a patterned bump directly formed on the chip body. The patterned bump has at least two different upper and lower plane patterns. A top surface of each of the metal bumps is higher than a height position on which the upper plane pattern is. When the chip structure is ground to the height position, the ground tops of the metal bumps and the upper plane pattern are flush. Therefore, detecting whether the upper plane pattern is exposed determines whether all the metal bumps are exposed and flush to each other to avoid insufficient grinding depth or over-ground.

Abstract: A fan-out package structure of an image sensing device includes an image sensing unit having an image sensor with opposite sensing surface and connecting surface, a spacer layer surrounding a central portion of the sensing surface, and a light-transmitting cover plate disposed on the spacer layer spaced apart from and covering the sensing surface. An image signal processor is disposed on the connecting surface. A redistribution layer covers the image signal processor and the connecting surface, and includes a fan-out area. An encapsulation layer is disposed on the fan-out area, surrounds and covers an outer periphery of the image sensing unit, and allows a top surface of the light-transmitting cover plate to be exposed. A method of manufacturing a fan-out package structure of an image sensing device is also disclosed.

Abstract: A package structure and a manufacturing thereof are provided. The package structure includes a base, a chip, a control element and an underfill. The chip is disposed on the base and includes a recess, and the recess has a bottom surface and a sidewall. The control element is disposed between the base and the chip and disposed on the bottom surface of the recess, and a gap exists between the control element and the sidewall of the recess. The underfill is disposed in the recess. The chip and the control element are electrically connected to the base respectively.

Abstract: A package structure including a first die, an encapsulant, a first circuit structure, a second circuit structure, a conductive connector, a second die, and a filler is provided. The encapsulant covers the first die and has a first surface and a second surface opposite to each other. The first circuit structure is disposed on the first surface. The second circuit structure is disposed on the second surface. The conductive connector penetrates the encapsulant. The second die is disposed on the second circuit structure. The second die has an optical signal transmission area. The filler is disposed between the second die and the second circuit structure. An upper surface of the second circuit structure has a groove. The upper surface includes a first area and a second area disposed on opposite sides of the groove. The filler directly contacts the first area. The filler is disposed away from the second area.

Abstract: A package device and a manufacturing method thereof are provided. The package device includes a substrate, a plurality of conductive pillars, at least one bridge chip, a photosensitive encapsulation layer, a redistribution layer, and at least two active chips. The conductive pillars and the bridge chip are disposed on the substrate. The photosensitive encapsulation layer surrounds the bridge chip and the conductive pillars, in which a distance between a top surface of the bridge chip and a top surface of the photosensitive encapsulation layer is less than a distance between a top surface of one of the conductive pillars and the top surface of the photosensitive encapsulation layer. The redistribution layer is disposed on the photosensitive encapsulation layer, the active chips are disposed on the redistribution layer, and the bridge chip is coupled between the active chips.

Abstract: A package device and a manufacturing method thereof are provided. The package device includes a substrate, a plurality of conductive pillars, a redistribution layer, at least one bridge chip, at least two active chips, an encapsulant, and an underfill layer. The conductive pillars are disposed on the substrate side by side, the redistribution layer is disposed on the conductive pillars, and the bridge chip is disposed between the substrate and the redistribution layer. The active chips are disposed on the redistribution layer, the bridge chip is coupled between the active chips, and the encapsulant is disposed on the redistribution layer and surrounds the active chips. The underfill layer is disposed between adjacent two of the conductive pillars and between one of the conductive pillars and the bridge chip.

Abstract: A semiconductor packaging assembly includes a redistribution layered structure having a plurality of device regions and a plurality of cutting regions separating the device regions, a plurality of recess structures respectively formed in the cutting regions, a plurality of chips respectively disposed in the device regions, and an encapsulating layer formed on the redistribution layered structure to fill the recess structures and enclose the chips.

Abstract: A semiconductor package has a substrate, a chip and an encapsulation. The substrate has a dielectric layer, a copper wiring layer and a solder resist layer formed thereon. The copper wiring layer is formed on the dielectric layer and is covered by the solder resist layer. The solder resist layer has a chip area defined thereon and an annular opening formed thereon. The annular opening surrounds the chip area and exposes part of the copper wiring layer. The chip is mounted on the chip area and is encapsulated by the encapsulation. Therefore, the semiconductor package with the annular opening makes the solder resist layer discontinuous, and the concentration stress is decreased to avoid a crack formed on the solder resist layer or the copper wiring layer when doing thermal-cycle test.

Abstract: A test head assembly for a semiconductor device has a carrier, a pin seat and a test wire assembly. The carrier is formed in an L shape and has a lateral board, a perpendicular board and a opening formed through the perpendicular board. The pin seat is mounted in the corresponding opening. The test wire assembly has a test head, a plurality of connectors and a plurality of test wires. The test head is mounted on an outer sidewall of the lateral board and connected to the pin seat through the test wires and the connectors. Therefore, the pin seat is mounted on the perpendicular board of the L-shaped uprightly and the test head is mounted on the lateral board. The pin seat and the test head are not parallel to each other, and a lateral size of the test head assembly is reduced to increase the space usage.

Abstract: A chip-middle type fan-out panel-level package (FOPLP) has a routing layer, a polyimide layer formed on the routing layer and having a plurality of pillar openings and a chip opening, a plurality of metal pillars mounted on the routing layer through the corresponding pillar openings, a chip mounted on the first routing layer through the chip opening and a molding compound formed on the polyimide layer to encapsulate the metal pillars and the chip. The polyimide layer is used to control the warpage of the FOPLP. The polyimide layer is formed inside the FOPLP and the chip is directly mounted on the first routing layer through the chip opening, so a height of the FOPLP is not increased when the first PI layer is added.

Abstract: Provided is an integrated antenna package structure including a chip, a circuit structure, a shielding body, an encapsulant, a first antenna layer, a dielectric body, and a second antenna layer. The circuit structure is electrically connected to the chip. The shielding body is disposed on the circuit structure and has an accommodating space. The chip is disposed in the accommodating space of the shielding body. The encapsulant is disposed on the circuit structure and covers the chip. The first antenna layer is disposed on the circuit structure and is electrically connected to the circuit structure. The dielectric body is disposed on the encapsulant. The second antenna layer is disposed on the dielectric body. A manufacturing method of the integrated antenna package structure is also provided.

Abstract: A sensor includes a first chip, a dam structure and a cover. The first chip includes a substrate, a sensing area and a low-k material layer. The sensing area is located on the surface of the substrate. The low-k material layer is located in the substrate. The dam structure is located on the first chip. The dam structure covers the edge of the low-k material layer. The cover is located on the dam structure and covers the sensing area. A manufacturing method of a sensor is also provided.

Abstract: A semiconductor package comprising plurality of bumps and fabricating method thereof. The package has a chip, a plurality of first and second bumps, an encapsulation, a redistribution. The chip has a plurality of pads and an active area and the active surface has a first area and a second area surrounding the first, the pads formed on a first area of the active surface, each first bump formed on the corresponding pad. The second bumps are formed on the second area, each second bump has first and second different width layers. The encapsulation encapsulates the chip and bumps and is ground to expose the bumps therefrom. During grinding, all of the first bumps are completely exposed by determining a width of an exposed surface of the second bump to electrically connect to the redistribution is increased. Therefore, a shallow-grinding or over-grinding does not occur.

Abstract: A stacked semiconductor package has a substrate, a first chip, at least one spacer, a second chip and an encapsulation. The first chip and the second chip are intersecting stacked on the substrate. The at least one spacer is stacked on the substrate to support the second chip. The encapsulation is formed to encapsulate the substrate, the first chip, the at least one spacer and the second chip. The at least one spacer is made of the material of the encapsulation. Therefore, the adhesion between the at least one spacer and the encapsulation is enhanced to avoid the delamination during the reliability test and enhances the reliability of the stacked semiconductor package.