Abstract: An analog switching circuit may be implemented with MESFETs without forward biasing the switching device, and is applicable to JFET switches in general. Switching currents are provided from a nominal input line which closely tracks the true analog input voltage, but is segregated therefrom. A current supply fed from the nominal input line provides transient charging current to the gate of the switching transistor during the switching transition from OFF to ON states. Voltage setting devices hold the gate and source of the enhancement-mode current supply at approximately the nominal supply voltage level when the switching transistor is ON, while a control section holds the gate and source of the current supply device at a negative reference voltage level when the switching transistor is OFF. In either case, the current supply device is inhibited from delivering gate current to the switching transistor during steady state operation.

Abstract: A voltage reference circuit is described which is capable of providing either an internally generated voltage having a trimming capability, or an externally generated voltage, with the use of only two pins. The internal voltage is connected through an interrupt circuit to an input/output terminal, which can also receive an externally generated voltage. A trimming terminal is used to apply trimming voltage signals to adjust the internally generated voltage. To convert from the internal to the external voltage source, an interrupt voltage is applied to the trimming terminal which is outside of the normal trimming voltage range. This interrupt voltage actuates an interrupt circuit to interrupt the connection between the internal voltage source and input/output terminal, leaving the output terminal available for the external voltage source.

Abstract: A carrier for an integrated circuit (IC) can has a plurality of low profile symmetrically distributed flexible arms extending from the carrier base with small hook projections for engaging a flange on the perimeter of the can. The low arm profile enables information to be printed on the side of the can while it is in the carrier. The symmetrical distribution of the flexible arms imparts an even load upon the can to prevent bending of the leads. The carrier base has round holes for receiving electrical leads projecting from the can to minimize the scraping of the leads during insertion and removal of the can from the carrier.

Abstract: A digital-to-analog converter (DAC) ladder segment is disclosed in which diode networks are introduced into the ladder step circuits. Each diode network includes a control diode which controls the flow of current through the network in accordance with a signal from an associated actuating circuit, which in turn is controlled by an input digital signal. In one embodiment, the control diodes are connected in series with resistors, with the diodes and resistors scaled so that their respective bit circuits conduct desired current levels. In another embodiment, the control diodes have equal scalings and are connected in series with respective resistors and second diodes which are called so that their step circuits conduct the desired currents. In a third embodiment, current sources are provided which supply currents to the second diodes in amounts that permit the second diode and the resistors for the various step circuits to have substantially equal scalings.

Abstract: An improved input current compensation circuit is provided for a dual branch amplifier, particularly an amplifier employing superbeta transistors. The compensation circuit has a superbeta compensation transistor which is matched with the superbeta amplifier transistors, a bipolar transistor connected across the superbeta transistor in a manner analogous to a voltage limiting circuit in the amplifier section, and current sources which provide operating currents to both the superbeta and bipolar compensation transistors. The base current of the superbeta compensation transistor is mirrored to the bases of the superbeta amplifier transistors, and the superbeta transistors, bipolar transistor and current sources in the compensation section are scaled relative to corresponding elements in the amplifier section so that the superbeta amplifier transistor base currents are substantially compensated by current mirrored from the compensation circuit.

Abstract: An active load circuit for operational amplifiers and the like is described which provides an improved common mode rejection ratio and common mode voltage range, and alleviates transistor saturation and cut off problems during maximum slew rates. Drive currents from the operational amplifier or other circuit are transmitted directly through respective load resistors, thereby reducing voltage offsets which degrade common mode rejection ratio. At the same time the absolute voltage levels at the operational amplifier or like circuit are reduced, thereby increasing the common mode voltage range. A pair of active load transistors are supplied with current from current sources independent of the amplifier transistors, and deliver their respective currents to the same resistors which receive the amplifier currents. An output is taken from one of the load transistors without connecting to either of the amplifier transistors.

Abstract: A test socket for a leadless chip carrier is disclosed in which a clamp is pivotally mounted to a base member, such that the carrier can be inserted into a recess in the base member and the clamp pivoted closed to lock the carrier in place. The clamp includes a set of arms which engage corresponding brackets on the base to progressively secure the carrier and chip as the clamp is rotated either clockwise or counterclockwise. The clamp makes direct contact with the chip to assure a good electrical connection with underlying electrical contact springs.

Abstract: A temperature insensitive voltage reference is described which can advantageously be implemented using standard CMOS processing techniques. A pair of parasitic bipolar transistors are coupled with appropriate resistors to produce a voltage with a temperature coefficient that is equal in value but of opposite polarity to a zener diode voltage-temperature coefficient. This voltage is then combined with a zener diode voltage to yield the desired output reference voltage.

Abstract: A CMOS output drive circuit has two field effect transistors (FETs) implemented with a CMOS process and characterized by parasitic bipolar transistors. The back-gates of the two transistors are tied together, such as by forming the devices in a common well, and the back-gate of the second FET is also connected to prevent its associated parasitic bipolar transistor from conducting. Quiescent loads are applied to the two FETs so that their voltages are comparable during low output loading, resulting in a drive circuit with high input impedance and high output voltage swing. The output terminal is taken from the first FET, the voltage of which becomes unbalanced from the second FET at relatively high output loads, turning on the parasitic bipolar transistor for the first FET. This gives the drive circuit a desirably high input impedance and low output impedance for heavy output loads.

Abstract: A temperature compensated voltage reference circuit in which a compensation current is generated by establishing a current through a passive impedance element which varies with temperature in accordance with the transistor voltage equation. This current is proportionately reflected into the output impedance circuit associated with the voltage reference, where it compensates for temperature induced voltage variations. The passive impedance element is adjustable to correct for processing variations, and the compensation circuit requires no voltage supplies other than those typically provided for the reference circuit by itself.

Abstract: An output circuit amplifier has first and second stage amplifying transistors with an impedance circuit connected between the base of the first stage transistor and the collector-emitter circuit of the second stage transistor to draw current from the first stage transistor base, thereby keeping both transistors out of saturation. The impedance circuit establishes a voltage drop between the two transistors such that large output voltage swings are enabled at an output terminal connected to the second stage transistor. The collector-emitter circuit of the first stage transistor is connected directly to a positive voltage bus to avoid further saturation problems.

Abstract: An analog multiplier circuit for multiplying X and Y input voltage signals and using two differential amplifiers to produce a multiplied output, in which separate pairs of transistors provide base drive currents to the amplifier transistors, one pair being associated with each amplifier. Trimming voltages are applied between the bases of each transistor pair to independently adjust the base voltage offsets. Nonlinearities between the multiplier output and the X input are reduced by appropriate trimming of the transistor base voltage differentials. Each of the differential amplifier transistors has a common base connection with a matching transistor that carries a current which is complementary to the amplifier transistor current with respect to the Y input signal, thereby reducing output nonlinearities with respect to the Y input signal by making the total base drive currents of both transistors substantially independent of the Y voltage signal.

Abstract: A digital control amplifier is provided as a unitary monolithic device to control the transfer function of an analog signal in response to a digital control, such as from a digital computer. A current transfer cell is employed which uses an amplifier circuit having transistors of like polarity, and is capable of both attenuation and greater than unity amplification of an input analog signal. A digital-two-analog converter is integrated into the system and employs a series of current dividers which enables a common reference current to be used for each bit of the converter. A current reference circuit for the converter employs a band gap voltage regulator with a temperature compensation design that varies the control signal applied to the current transfer cell to compensate for temperature-induced variations in the output of the cell.

Abstract: A JFET differential amplifier stage in which the gate-drain voltage of each JFET is kept at least as great as the pinchoff voltage (V.sub.p), but preferably close to V.sub.p so as to reduce the effects of impact ionization and generation currents on the amplifier's input bias currents. The JFETs are supplied with currents which force their gate-source voltages to at least 0.5 V.sub.p. A second pair of JFETs are cascoded with the first pair and also develop gate-source voltages of at least 0.5 V.sub.p. The gate-source terminals of the second pair are connected in a loop with the source-drain terminals of the first pair, thereby forcing the gate-drain voltages of the first pair to at least V.sub.p, the minimum voltage necessary to hold the first pair in a desired saturated state. A third pair of JFETs is connected to buffer the first pair from capacitances developed at the gates of the second pair without effecting the AC operation of the circuit.

Abstract: An integrated current mirror circuit in which a compensation transistor is added in each stage of the mirror to compensate for the base-substrate leakage currents of the other transistors in the mirror circuit and to keep the circuit operative even at high temperatures and low current levels. Each compensation transistor is matched with the other transistors in its stage and has its collector-emitter circuit connected between a voltage source terminal and the common base connection of the other transistors. The base of each compensation transistor is unconnected to the remainder of the circuit but exhibits a base-substrate leakage current which is employed in the compensation scheme.

Abstract: An improved input current compensation circuit is provided for a superbeta transistor amplifier. The circuit has a pair of compensation transistors which simulate the amplifier transistors and support a base current which is mirrored back to the amplifier circuit to cancel the input currents thereof. The compensation transistors are supplied with base current by a control transistor. A special voltage control circuit is provided to establish controlled collector-emitter voltages for the compensation transistors independent of the control transistor, thereby decoupling the compensation transistors from the uncertain effects of the control transistor's base-emitter voltage. The control circuit is connected from the collector of one compensation transistor to the emitter of the other, and is provided with primary and secondary current sources to establish a current flow that sets up a desired bias for the control transistor and results in a near exact cancellation of input bias current.

Abstract: A plurality of carriers for integrated circuit devices are each uniquely coded so as to be recognizable by an automatic decoding apparatus. The devices are tested and the test results accurately correlated with the appropriate devices by recording the test results for each device, reading the identification code for each carrier in the same sequence in which the devices are tested, and then correlating the test results with the device identifications. A prior art requirement of maintaining the carriers in the order in which they were tested is eliminated once the carriers have been thus identified. In a preferred embodiment the carrier body is provided with an array of perforations, the transmission of light through each perforation being blocked by a breakable membrane. Each carrier is coded by breaking a selected combination of its membranes to establish a unique binary identification code for each carrier.

Abstract: A bias circuit for an FET switch in which a pinch-off voltage is generated and sets up a current through a first resistor. The current is reflected through a second resistor to establish a voltage differential across the second resistor which is then imposed across the gate-source terminals of the switch FET when it is desired to turn the switch OFF. The relationship of the turn-off voltage imposed across the switch FET to its pinch-off voltage is determined by the ratio of the resistance values of the two matched resistors, which ratio is independent process and temperature. The switch bias circuit thus offers highly reliable operation and at the same time a greatly reduced power consumption.

Abstract: An I.C. integrator circuit is provided with an active tuneable element by which a precise integrator time constant can be established, despite variations in the values of individual circuit components. A plurality of integrator circuits are connected in an overall frequency responsive circuit, each integrator circuit having a input transconductance stage, an output integrating stage, and an adjustable intermediate conditioning stage, the latter stage preferably comprising a Gilbert multiplier circuit. The time constant of each integrator circuit is controlled by the conditioning stage, which in turn is under the control of a bias circuit common to all of the integrator circuits. A desired net frequency response characteristic can be achieved by simple adjustments to the common bias circuit, despite normal tolerances and variations among individual integrator circuits.

Abstract: An improved start-up circuit is provided for self-biased circuits of the type connected to a supply voltage and having biasing currents stable at two operating points at which the biasing currents are either zero or nonzero in value when the supply voltage is nonzero and having sufficient regenerative feedback to raise the level of the biasing currents to the nonzero value when an initial current is provided to the circuit. The start-up circuit includes a resistive element which provides a current path from the supply voltage to the self-biased circuit and a transistor element, responsive to the current flow through the path for supplying an initial current to the self-biased circuit, whereupon the regenerative feedback causes the circuit to draw a current related to the biasing current through the current path as the biasing currents reach the nonzero operating point.