Abstract: A current control circuit which can be used to provide starting current during the build-up of an input voltage, and terminate the starting current when the input voltage has reached a predetermined level. The preferred embodiment employs three FETs and one bipolar transistor, located in a total of only two isolation pockets on an integrated circuit chip. The first FET, which is scaled to operate in its saturated region while the second FET is in its resistive region, transmits a current received from the second FET as an output starting current during the initial portion of the input voltage build-up. During this time the second FET holds the gate-source voltage of the first FET to a level less than its pinch-off voltage. The third FET has its gate and source terminals connected in parallel with the first FET, and its drain connected to the base of the bipolar transistor, which is also connected to shunt current away from the first FET when appropriately gated.

Abstract: An improved analog track and hold circuit has a glitch-free output as the circuit switches between the tracking and the holding of an input analog signal. The circuit is of the type having a capacitor for storing an analog voltage, a transconductance amplifier for producing a charging current for the capacitor proportional to the analog voltage, a current switch for connecting and disconnecting the charging current for the capacitor, and an output circuit to buffer the capacitor voltage to the output. The improvement includes a diode array establishing first and second reference nodes across the capacitor. The diodes in the array clamp the first and second nodes to fixed incremental voltage values greater and lesser, respectively, than the capacitor voltage as the circuit tracks the analog voltage, and to fixed incremental voltage values lesser and greater, respectively, than the capacitor voltage, as the circuit holds the analog voltage.

Abstract: An electronic circuit simulates the direct current characteristics of the hybrid transformer portion of the telephone system call-handling equipment. The circuit is connected across a two-wire telephone subscriber loop and supplies a loop current that is proportional to the difference between a constant current and a reference current. The circuit contains a voltage sensing circuit which senses the voltage across the loop and transfers the sensed voltage across a reference resistor, thereby developing a reference current through the resistor which is proportional to the voltage across the subscriber loop. An integral current generator supplies a constant current to the circuit. An integral current subtractor, connected between the output of the voltage sensing circuit and the current generator subtracts the constant current from the reference current. The resulting current forms the input current to an integral current amplifier.

Abstract: A junction FET switching circuit and method in which the gate-source voltage of the switching FET is varied with changing temperature so as to maintain the FET channel resistance substantially constant over a selected temperature range. An offset is introduced to the gate-source voltage to permit adequate voltage variation over the temperature range.

Abstract: A high current capacity junction field effect transistor, or JFET, is provided with certain special circuitry so that it may be rapidly switched on and off, and is protected against fault currents. The gate electrode of the large switch JFET is controlled by a circuit including four additional JFET's of somewhat smaller size, arranged in two pairs, with a transistor interconnecting one of the pairs of JFET's. The first pair of JFET's permits the rapid charging of the sizable gate capacitance of the switch JFET as it is being turned off, with the second series connected pair of JFET's of smaller current carrying capacity serving to continue the current flow, and maintain the gate electrode of the switch JFET at the desired "pinch-off" voltage, When the switch JFET is being turned on, the transistor is initially energized by the differing current capacities of the two transistors making up the second, current limiting air of JFET's mentioned above, to rapidly discharge the large switch JFET capacitance.

Abstract: A voltage comparator is provided with a high speed output stage having positive feedback. The output stage uses two transistors, both in grounded emitter circuit configurations, and two current sources supplying current to two different nodes associated with the two transistors. One node is connected to the base of a first one of the two transistors and to the collector of the second transistor. The other node is at the junction of the base of the second transistor and a resistor connected to the collector of the first transistor. An input comparator circuit selectively diverts current from the base of the second transistor. When the current is diverted from the base of the second transistor, the first transistor is turned on and the second transistor is turned off, as its base is starved of any drive. When the input voltage changes so that the current is no longer diverted, current is supplied first through the resistor to the collector of the first transistor and then to the base of the second transistor.

Abstract: A simplified temperature stabilized circuit provides a current which is proportional to a variable voltage by the use of branching transistor circuitry which fixes the voltage level of the supplied current, and controls its magnitude. The variable voltage is supplied through a reference resistor to the emitter of a first junction transistor having its base connected to the base of an identical junction transistor having its emitter grounded, thereby fixing the input voltage to the first transistor at a virtual ground potential. A third identical transistor has its base and emitter connected in parallel with the first transistor and carries an equal amount of current. Current derived in parallel from the first and second transistor is positively proportioned relative to the current flowing in the collector path of the third transistor by a pair of mirror-connected transistors having suitable relative areas and load resistors.

Abstract: An integrated circuit for rapidly charging a capacitive holding device to a voltage level within a predetermined range of acquired samples. One or more supercharging circuits can be provided to supplement the input signal in charging the signal holding device when the input signal by itself is not capable of providing enough current for rapid operation. The supercharging circuits compare the input signal with the held signal and provide supplemental charging current when the differential between these signals exceeds a predetermined threshold amount. Above this threshold the supplemental charging current varies progressively and preferably linearly with the signal differential, until a terminal point is reached above which the supercharging current remains constant. Provision is also made for inhibiting leakage of the held signal back into the charging circuit.

Abstract: The outputs of individual stages in a digital to analog converter are each trimmed by independent circuitry which includes a plurality of transistors connected to a common output terminal, the physical dimensions of each transistor being scaled in proportion to desired levels of current flow, and selectable switches connected in circuit with each of the transistors. Selectable switches are actuable to produce an output trimming current of a desired magnitude, which current is used to correct the untrimmed stage output. The invention includes circuitry for controlling the polarity of the trimming current relative to the stage, and for selectively expanding or contracting the trimming range to optimize the trimming currents for the particular characteristics of the converter. A favorable balance between trimming accuracy and the area occupied by the trimming circuitry is attained by the use of both emitter-scaled and multicollector transistors in the trimming circuits.

Abstract: Novel apparatus is described for controlling the application of circuit adjustment signals to an electrical circuit device. The same device leads are used in an operating mode with input signals in a first range, and in an adjustment mode with input signals in a second range, the two ranges being mutually exclusive.An exemplary embodiment is directed toward trimming a digital to analog converter. A plurality of trimming elements are provided with an equal number of two-terminal actuating devices, which are arranged in a matrix such that each pair of terminals is connected in circuit with a unique pair of input leads. The devices actuate their associated trimming elements in response to the application of actuating signals, exceeding a threshold level greater than the level of the binary input signals, to their respective lead pairs. The leads are thereby capable of a dual mode operation, with one mode for normal converter operation and the other mode for setting up desired trim circuits.

Abstract: A digital to analog converter with bit circuits arranged in binary order, in which a supplemental current circuit is added to selected bit circuits to enable convenient and efficient conversion from binary to BCD operation. Supplemental BCD currents are controlled by a bias circuit which automatically increases the BCD bit circuit bias to a level at which the full-scale BCD output current is substantially equal to the full-scale binary output current.

Abstract: There is disclosed a dual mode amplifier for use as the output amplifier of a sample and hold circuit. The dual mode amplifier described by the invention is controlled by a sample and hold gate. In one of its modes the characteristics of the amplifier are optimized for best slew rate and transient performance, while in the other mode the amplifier characteristics are optimized for settling time.

Abstract: A digital to analog converter is disclosed wherein two current outputs are provided, one the complement of the other. The digital to analog converter includes a novel two branched, symmetric, transistor switching circuit as well as an improved electrical n-bit weighting network which has ports for communicating weighted signal segments to connected transistor switching circuits. Logic inputs to the switching circuits determine whether an output signal is to be supplied in a first output summing line or a second, complementary, output summing line, both of which have high output impedance and high output voltage compliance which defines true current output.

Abstract: A circuit for interfacing a digital to analog converter with input signals from three different logic systems, whereby appropriate threshold switching signals compatible with each logic system are presented to the converter when the proper logic control signal is applied to the circuit. The first logic system is characterized by logic control signals within a first voltage range, and switching thresholds which differ from the logic control signals by a fixed increment; the second system by logic control signals within a second voltage range higher than the first range, and switching thresholds equal to a fixed proportion of the logic control signal; and the third system by a substantially constant switching threshold for a predetermined positive supply voltage level.

Abstract: An integrated circuit including an FET and an analog for cancelling input current that would otherwise be required to supply the FET gate leakage current. The analog establishes a leakage current the magnitude of which is a substantially fixed proportion of the FET leakage current over a given operating range, and employs proportional current mirror means referenced to the analog leakage current to supply the FET leakage current and thereby substantially cancel the input bias current. In a preferred embodiment the analog comprises a lateral PNP multi-collector transistor with one collector connected to its base to establish a reference current, another collector providing the cancellation current, and its base voltage tracking the FET gate voltage so that the two leakage currents remain substantially equal. An analog FET may also be employed to cancel gate-to-drain and gate-to-source leakages. A description of the invention as applied to an operational amplifier is given.

Abstract: A symmetric, two-branched transistor switching circuit is disclosed wherein steering current is fed to a node between the two branches. A logic input signal controls the electrical balance between the two branches controlling the flow of steering current from one branch to the other and back, depending upon two discrete logic input levels. The two-branched circuit is connected to a pair of loads, one associated with each circuit branch as well as to a common node which may be connected to an auxiliary circuit. By a balanced circuit configuration and supplying properly regulated bias during a logic input transition, the effects of parasitic capacitance, which normally delays switching times, may be reduced, thereby permitting the switching of very low levels of current, i.e. on the order of 1 or 2 microamperes at speeds comparable to those obtained when switching 1 or 2 ma. An auxiliary circuit which may be connected to the common node of the circuit is an electrical ladder which decrements current.

Abstract: Disclosed is a multistage resistor and transistor network for use in forming a plurality of weighted signals and which utilizes a conventional R-2R ladder network connected to a single reference means for decrementing the reference signal into weighted signals and a remainder signal. Rather than terminating the remainder, as in the prior art, at least one slave ladder network is connected for receiving the remainder signal and decrementing the remainder signal into a plurality of decrementally weighted signals to be taken in parallel with the decrementally weighted signal segments of a master ladder.