Abstract: A configurable architecture, hybrid analog/digital delay locked loop and technique with fast open loop digital locking for integrated circuit dynamic random access memory (DRAM) devices and devices incorporating embedded DRAM. The DLL design and technique disclosed employs a hybrid analog/digital delay line, but does not use conventional closed loop architecture during the digital phase of the locking process.

Abstract: An output driver calibration circuit includes a programmable drive strength output pullup driver including a strongest transistor and a number of other transistors, a programmable drive strength output pulldown driver including a strongest transistor and a number of other transistors, and a calibration circuit for generating a number of control signals for controlling the transistors in the output pullup driver and the transistors in the output pulldown driver, wherein the control signals are generated simultaneously, except for two the strongest driver transistors.

Abstract: A bus driver circuit divides an internal data bus for an integrated circuit memory into at least two groups, designated by speed. A faster group of data lines and a slower group of data lines are placed in an interleaved fashion in order to provide a two group shielding solution. At the earliest opportunity following the reception of a read command, the data from memory banks in the memory is sorted into these two groups. For a DDR3 memory, the sorting method is based on the A2 column address, known as C2. All of the data is brought out of the banks in parallel and sorted as it enters the main amplifiers. These main amplifiers are also divided into two groups, faster and slower. Each amplifier then connects to a data line (G-line) of the same group. The clock assigned to the fast group fires right away, thereby connecting the data associated with the fast amplifiers to the fast data group. This data group then proceeds to the output buffers through the entire data path as fast as possible.

Abstract: Using the tail level referencing for an inverter stage immediately following a differential amplifier provides trip point tracking with the variations in magnitude of the output level swings on the differential amplifier stage output over the operating range of the circuit. When the tail voltage increases and the VOL of the differential stage increases, the trip point of the receiving inverter also increases. When the tail voltage decreases and the VOL of the differential amplifier goes lower, the trip point of the inverter decreases. An additional benefit is provided by the tail connection to the inverter. Faster switching of current from the right side to the left side of the differential amplifier occurs due to the tail node voltage being raised momentarily by a transistor in the inverter stage when the input of the inverter stage transitions high.

Abstract: A multi-bank block architecture for integrated circuit memory devices which effectively reduces the total length of the datapath for a given input/output (I/O) from the memory cells in the memory array to the actual device I/O pad. In accordance with the present, a memory block in a memory device is effectively divided into two or more banks, and between these banks an additional non-shared sense amplifier band is added as a sense amplifier cannot be shared across a bank boundary. Within this multi-bank block, separate data paths are provided for the banks with the column (Y-Select) lines being common.

Abstract: An asymmetric data path position and delays technique enabling high speed access in integrated circuit memory devices which is asymmetric in terms of the delay from the array to the I/O buffers based on the position relative within a known starting address of a pre-fetch field. In accordance with the technique of the present invention, the delay is not only asymmetric in terms of its physical length, but also in the number of pipeline stages and the clocks that control them and can also be asymmetric in terms of the column address required to access each section of the array and its designated pre-fetch field.

Abstract: A twin cell architecture for dynamic random access memory (DRAM) devices and those devices incorporating embedded DRAM utilizing an open bitline configuration is disclosed. The twin cell architecture disclosed has significant advantages over conventional designs in terms of power, radiation hardness and speed and does not require intermediate supply voltage bitline precharge while allowing for 6F2 memory cell layouts.

Abstract: A high-speed, low-power input buffer for an integrated circuit device in which the input voltage (VIN) is coupled to both a pull-up and a pull-down transistor. In accordance with a specific embodiment, the input buffer utilizes a reference voltage input (VREF) during a calibration phase of operation but not when in an active operational mode. A maximum level of through current is supplied when VIN=VREF with lower levels of through current at all other VIN voltages. In an integrated circuit device incorporating an input buffer as disclosed, two (or more) input buffers may be utilized per device input pin.

Abstract: Using the tail level referencing for an inverter stage immediately following a differential amplifier provides trip point tracking with the variations in magnitude of the output level swings on the differential amplifier stage output over the operating range of the circuit. When the tail voltage increases and the VOL of the differential stage increases, the trip point of the receiving inverter also increases. When the tail voltage decreases and the VOL of the differential amplifier goes lower, the trip point of the inverter decreases. An additional benefit is provided by the tail connection to the inverter. Faster switching of current from the right side to the left side of the differential amplifier occurs due to the tail node voltage being raised momentarily by a transistor in the inverter stage when the input of the inverter stage transitions high.

Abstract: A duty cycle correcting circuit for an integrated circuit memory automatically corrects the duty cycle of an input clock by measuring the relative difference between the high time and low time of the input signal and using this measurement to achieve a same-frequency, duty cycle adjusted output signal. The duty cycle correcting circuit includes a duty cycle adjust circuit that uses two series-connected N-channel transistors to control the pull-up slew rate of a signal and another N-channel transistor to control the pull-down slew rate of the same signal, two dual-slope integrator circuits, and input and output signal buffering.

Abstract: A data capture circuit includes strobes that track input data even when conditions arise that cause the differences in skew from interpreting data state ones and zeros. This is accomplished whether these skews arise from reference voltage variation, data pattern loading, power supply droop, process variations within the chip itself, or other causes. The differential input strobes of the data capture circuit are input into individual input buffers, each compared against a reference voltage individually, as well as a data input pin. The outputs from these buffers are maintained separate from each other all the way to the point where the input data is latched. In latching the input data, data ones are latched entirely based on input signals derived from a rising edge (both strobes and data), and zeros are latched entirely based on input signals derived from a falling edge (both strobes and data).

Abstract: A column repair circuit uses a system of circuits that automatically stops the shifting of register contents independently of the number of bits to be shifted. The circuit is only dependent on the number of bits in a column address repair block. By adding shift register positions to one end of each shift register chain, a dedicated block of bits is used to detect the end of the shift chain without explicitly knowing the length of the chain. The shift register positions provide a hard-programmed code that can be used to stop the shifting of data automatically. The shift register positions also provide a space for hard-programmed code bits that can be examined to determine when the shift process ends. A shift chain can be controlled with a controller so long as the information is organized into groups of ‘k’ bits. The controller only requires information regarding the value of the number ‘k’ and the pre-programmed stop code in order to control any number of bits in a shift chain.

Abstract: A circuit and technique for adjusting and accurately controlling clock duty cycles in integrated circuit devices in which only N-channel current regulating transistors are used in the voltage-controlled inverters and both the rising and falling edges can be adjusted by cascading two such inverters. The potential for cascading of these inverters allows for additional accuracy to be achieved.

Abstract: A DRAM refresh period adjustment technique based on the retention time of one or more unused memory cell(s) having characteristics very similar to the characteristics of the memory cell(s) with the shortest retention time used in the DRAM array. In a particular implementation of the technique of the present invention, the refresh period of a DRAM array is adjusted through the use of one or more of the DRAM bits that fail to meet the retention time requirement and have, therefore, been replaced by redundant DRAM bits. These replaced bits are then used to indicate the refresh period for the DRAM is the maximum it can be for the DRAM under then current operating conditions.

Abstract: A DLL circuit uses a rising edge DLL to align the rising edge of the output data to the system clock and a falling edge DLL to align the falling edge of the output data. The DLL circuit does not use the falling edge of the input clock to provide a reference for the falling edge DLL. The DLL circuit uses the rising edge of a first reference clock (a buffered version of the input clock) to align the rising edge of the output data. An additional DLL is used to generate a precise second reference clock that is delayed by exactly one-half period of the first reference clock to align the falling edge of the output data. Any variation in the duty cycle of the input clock or the input clock buffer does not effect the duty cycle of the output data.

Abstract: A duty cycle correcting circuit for an integrated circuit memory automatically corrects the duty cycle of an input clock by measuring the relative difference between the high time and low time of the input signal and using this measurement to achieve a same-frequency, duty cycle adjusted output signal. The duty cycle correcting circuit includes a duty cycle adjust circuit that uses two series-connected N-channel transistors to control the pull-up slew rate of a signal and another N-channel transistor to control the pull-down slew rate of the same signal, two dual-slope integrator circuits, and input and output signal buffering.

Abstract: A circuit provides the widest possible window for capturing data and preventing run-through in a FIFO register. The FIFO register includes two registers per I/O. Two FIFO input clocks are used, one for each FIFO register. When one FIFO clock is active, the other is automatically disabled. Initially, the circuit is reset such that one clock is active, and the other disabled. Upon receiving a valid READ command, a shift chain attached to the FICLK that is currently low begins counting the clock cycles. This eventually determines when the FICLK that is currently low can be enabled. The final enable is dependent upon the turning off the FICLK that is currently high. The FICLK that is enabled during the reset turns off a fixed delay after the falling edge of the YCLK associated with the READ command.

Abstract: A circuit provides the widest possible window for capturing data and preventing run-through in a FIFO register. The FIFO register includes two registers per I/O. Two FIFO input clocks are used, one for each FIFO register. When one FIFO clock is active, the other is automatically disabled. Initially, the circuit is reset such that one clock is active, and the other disabled. Upon receiving a valid READ command, a shift chain attached to the FICLK that is currently low begins counting the clock cycles. This eventually determines when the FICLK that is currently low can be enabled. The final enable is dependent upon the turning off the FICLK that is currently high. The FICLK that is enabled during the reset turns off a fixed delay after the falling edge of the YCLK associated with the READ command.

Abstract: A DLL circuit uses a rising edge DLL to align the rising edge of the output data to the system clock and a falling edge DLL to align the falling edge of the output data. The DLL circuit does not use the falling edge of the input clock to provide a reference for the falling edge DLL. The DLL circuit uses the rising edge of a first reference clock (a buffered version of the input clock) to align the rising edge of the output data. An additional DLL is used to generate a precise second reference clock that is delayed by exactly one-half period of the first reference clock to align the falling edge of the output data. Any variation in the duty cycle of the input clock or the input clock buffer does not effect the duty cycle of the output data.

Abstract: A circuit provides the widest possible window for capturing data and preventing run-through in a FIFO register. The FIFO register includes two registers per I/O. Two FIFO input clocks are used, one for each FIFO register. When one FIFO clock is active, the other is automatically disabled. Initially, the circuit is reset such that one clock is active, and the other disabled. Upon receiving a valid READ command, a shift chain attached to the FICLK that is currently low begins counting the clock cycles. This eventually determines when the FICLK that is currently low can be enabled. The final enable is dependent upon the turning off the FICLK that is currently high. The FICLK that is enabled during the reset turns off a fixed delay after the falling edge of the YCLK associated with the READ command.