Abstract: One semiconductor device includes a wiring board, a semiconductor chip, and an encapsulation body. The wiring board includes an insulating base, a conductive pattern that is formed on one surface of the insulating base, and a heat dissipation via that is connected to the conductive pattern. The heat dissipation via is provided so as to penetrate through the insulating base from one surface to the other surface, while being exposed from the lateral side of the insulating base. The semiconductor chip is mounted on the wiring board so as to overlap the conductive pattern. The encapsulation body is formed on the wiring board so as to cover the semiconductor chip.

Abstract: A switching regulator includes: a switching element that controlling supply of power supply voltage according to a control signal; a smoothing circuit smoothing the power supply voltage supplied via the switching element and supplying the smoothed power supply voltage as an output voltage to an output terminal; an error amplifier outputting an error signal according to a difference between the output voltage supplied to the output terminal and a reference voltage; a delta sigma modulation circuit generating a delta sigma modulation signal according to the error signal; and a power supply abnormality detection circuit outputting the delta sigma modulation signal as the control signal and detecting an abnormality in the power supply voltage based on the delta sigma modulation signal.

Abstract: A semiconductor device includes memory blocks MB1 and MB2 and redundancy determination circuit 25 that can enter a normal operation mode that accesses either memory block MB1 or memory block MB2 and a refresh mode that simultaneously accesses both memory block MB1 and memory block MB2. In response to normal memory cell NMC that belongs to at least one of memory blocks MB1 and MB2 being replaced by redundant memory cell RMC in the refresh mode, redundancy determination circuit 25 deactivates normal cell area NCA to which normal memory cell NMC that is a source of replacement belongs, and activates redundant cell area RCA to which redundant memory cell RMC that is to be replaced belongs and normal cell area NCA to which normal memory cell NMC that is not being replaced belongs.

Abstract: A semiconductor device comprises a semiconductor substrate, a first transistor including a gate insulating film and a gate electrode sequentially formed on the semiconductor substrate, a sidewall, an interlayer insulating film formed on the semiconductor substrate, and a contact plug which penetrates through the interlayer insulating film and reaches the semiconductor substrate. The sidewall is formed on a side surface of the gate electrode, and includes a first insulating film and a second insulating film formed on the first insulating film and containing a metal oxide different from the first insulating film.

Abstract: A semiconductor memory device includes a plurality of memory banks each including a plurality of circuit areas selected based on an address signal, any one of which is selected by a corresponding bank selective signal (source transistor control signals), and a selective activation circuit that, from among circuit areas included in a memory bank that is selected based on the bank selective signal, activates any one of the circuit areas based on the address signal, and deactivates at least one of rest of the circuit areas. According to the present invention, the power consumption can be reduced in an active state by a dynamic power control in response to an address signal, not by entire power control by an external command.

Abstract: A semiconductor device includes a wiring board, a first semiconductor chip mounted on the wiring board via a first adhesive member, and second semiconductor chip stacked on the first semiconductor chip via a second adhesive member. The first adhesive member is a die attach film having an adhesive layer formed on both surfaces of an insulating base, and the second adhesive member is an adhesive paste.

Abstract: A semiconductor device includes a stacked plurality of memory chips. The memory chips each include a plurality of memory banks, a plurality of read/write buses that are assigned to the respective memory banks, and a plurality of penetration electrodes that are assigned to the respective read/write buses and arranged through the memory chip. Penetration electrodes arranged in the same positions as seen in a stacking direction are connected in common between the chips. In response to an access request, the memory chips activate the memory banks that are arranged in respective different positions as seen in the stacking direction, whereby data is simultaneously input/output via the penetration electrodes that lie in different planar positions.

Abstract: Disclosed herein is a device that includes: a semiconductor substrate; plurality of first through-substrate vias each penetrating through the semiconductor substrate, a plurality of second through-substrate vias each penetrating through the semiconductor substrate, an insulating film formed over the semiconductor substrate, the insulating film including a first opening and a plurality of second openings, the first opening being located over the first through-substrate vias, and each of the second openings being located over a corresponding one of the second through-substrate vias.

Abstract: A method for manufacturing a stacked semiconductor memory device includes testing a plurality of memory chips to detect first defective addresses, programming optical fuses with first defective address information on each of the plurality of memory chips that have the first defective addresses, stacking the plurality of memory chips, testing the stacked memory chips to detect second defective addresses, and programming electrical fuses with second defective address information.

Abstract: A stacked semiconductor device is constructed by stacking in two levels: a lower semiconductor device having a wiring board, at least one semiconductor chip mounted on a first surface of the wiring board and having electrodes electrically connected to wiring by way of a connection means, an encapsulant composed of insulating plastic that covers the semiconductor chip and the connection means, a plurality of electrodes formed overlying the wiring of a second surface of the wiring board, and a plurality of linking interconnects each having a portion connected to the wiring of the first surface of the wiring board and another portion exposed on the surface of the encapsulant; and an upper semiconductor device in which each electrode overlies and is electrically connected to the exposed portions of each of the linking interconnects of the lower semiconductor device.

Abstract: To provide a semiconductor device with a wafer level package structure that allows for probing while reducing the area occupied by the pad electrodes. [Solution] In the present invention, the following are provided: a semiconductor chip (100) that has first and second pad electrodes (120a, 120b) disposed on the main surface thereof; insulating films (310, 330) that cover the main surface of the semiconductor chip (100); a rewiring layer (320) that is disposed between the insulating films (310, 330); and a plurality of external terminals (340) disposed on the top of the insulating film (330). The plane size of the first pad electrode (120a) and the second pad electrode (120b) differ from one another, and the first pad electrode (120a) and the second pad electrode (120b) are connected to any of the plurality of external terminals (340) via the rewiring layer (320).

Abstract: One semiconductor chip includes a substrate having insulation properties, a plurality of bump electrodes provided on one surface of the substrate, a plurality of recesses provided in the other surface of the substrate, and a solder layer disposed within the recesses. The recesses are formed such that the area of the opening decreases from the other surface side toward the one surface side of the substrate.

Abstract: [Problem] To provide a semiconductor device with a wafer level package structure that allows for probing while reducing the area occupied by the pad electrodes. [Solution] In the present invention, the following are provided: a semiconductor chip (100) that has first and second pad electrodes (120a, 120b) disposed on the main surface thereof; insulating films (310, 330) that cover the main surface of the semiconductor chip (100); a rewiring layer (320) that is disposed between the insulating films (310, 330); and a plurality of external terminals (340) disposed on the top of the insulating film (330). The plane size of the first pad electrode (120a) and the second pad electrode (120b) differ from one another, and the first pad electrode (120a) and the second pad electrode (120b) are connected to any of the plurality of external terminals (340) via the rewiring layer (320).

Abstract: Disclosed herein is a device that includes: a sense amplifier circuit activated in response to a first control signal; a first global bit line coupled to the sense amplifier circuit; a first local bit line; a first transistor electrically coupled between the first global bit line and the first local bit line, the first transistor being rendered conductive in response to a second control signal; a first memory cell; a first cell transistor electrically coupled between the first local bit line and the first memory cell, the first cell transistor being rendered conductive in response to a third control signal; and a control circuit producing the first, second, and third control signals such that the second control signal is produced after producing the third control signal and the first control signal is produced after producing the second and third control signals.

Abstract: A semiconductor device capable of increasing ON current while reducing channel resistance and allowing transistors to operate independently and stably, having a fin formed to protrude from the bottom of a gate electrode trench, a gate insulating film covering the surfaces of the gate electrode trench and the fin, a gate electrode embedded in a lower part of the gate electrode trench and formed to stride over the fin via the gate insulating film, a first impurity diffusion region arranged on a first side face, and a second impurity diffusion region arranged on a second side face.

Abstract: Disclosed herein is a device includes first and second memory mats. The first memory mat includes first and defective memory cells and first local bit lines coupled to a first global bit line. Each of the first local bit lines is coupled to associated ones of the first memory cells, one of the first local bit lines is further coupled to the defective memory cell. The second memory mat includes second and redundant memory cells and second local bit lines coupled to a second global bit line. Each of the second local bit lines is coupled to associated ones of the second memory cells, one of the second local bit lines is further coupled to the redundant memory cell. The device further includes a control circuit accessing the redundant memory cell when the access address information coincides with the defective address information that designates the defective memory cell.

Abstract: Semiconductor layers on active areas for transistors in a memory cell region (region A) and a peripheral circuit region (region B) are simultaneously epitaxially grown in the same thickness in which the adjacent semiconductor layers in region A do not come into contact with each other. Only semiconductor layer (10) in region B is also grown from the surface of a substrate which is exposed when only the surface of STI (2) in region B is drawn back, so that a facet (F) of the semiconductor layer 10 is formed outside the active area, followed by ion-implantation to form a high density diffusion layer (11) in region B. Accordingly, short circuit between semiconductor layers on source/drain electrodes of transistors in region A is prevented, and uniformity of the junction depth of the layer (11) of the source/drain electrodes including an ESD region in a transistor of region B is obtained, thereby restricting the short channel effect.

Abstract: A device includes first and second semiconductor chips. The first semiconductor chip includes an edge defining a periphery of the first semiconductor chip. The second semiconductor chip is greater in size than the first semiconductor chip. The second semiconductor chip is stacked over the first semiconductor chip so that the second semiconductor chip hangs over from the edge of the first semiconductor chip. The second semiconductor chip includes a plurality of wiring patterns including a first wiring pattern that positions over the edge of the first semiconductor chip, an insulating film which covers the wiring patterns and which includes on or more holes that expose one or more the wiring patterns, and one or more bump electrodes formed on the one or more the wiring patterns. Remaining one or ones of the wiring patterns is kept covered by the insulating layer and includes the first wiring pattern.

Abstract: A device includes a semiconductor substrate, a first penetrating electrode penetrating through the semiconductor substrate, a first test pad, and a first tri-state buffer coupled between the first penetrating electrode and the first test pad. The first tri-state buffer receives a buffer control signal at a control terminal thereof. The device further includes a buffer control circuit supplying the buffer control signal to the first tri-state buffer.

Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, a first insulating film region that is embedded in a trench formed on the semiconductor substrate, a gate electrode that covers a lower surface of the first insulating film region, and a gate insulating film that is provided between the gate electrode and the semiconductor substrate. The semiconductor device further includes a first diffusion region that covers a first side surface of the first insulating film region, a second diffusion region that covers a second side surface of the first insulating film region, and a third diffusion region that covers an upper surface of the second diffusion region. A selective element includes a field-effect transistor that is constituted by the gate electrode, the first diffusion region, and the second diffusion region, and a bipolar transistor that is constituted by the substrate and the second and third diffusion regions.