Abstract: An eventpoint chaining apparatus for generalized event detection and action specification in a processing environment is described. In one aspect, the eventpoint chaining apparatus includes a first processor which has a programmable eventpoint module with an input trigger (InTrig) input. The first processing element detects an occurrence of a first processor event (p-event) and produces an OutTrigger (OT) signal. The eventpoint chaining apparatus also includes a second processor which has a programmable eventpoint module with an input trigger (InTrig) input which receives the OT signal from the first processing element. The second processing element detects an occurrence of a second p-event and produces, in response to the OT signal received from the first processing element and the detection of a second p-event, an eventpoint (EP) interrupt signal.

Abstract: A coprocessor interface is described which provides a flexible degree of coupling with a host control processor. Specific methods are defined for architectures to make use of the interface for supporting client-server coprocessors (CSCOPs). A dynamic debug interface is used to provide a coprocessor interface which supports tightly coupled, loosely coupled and firmly coupled operation.

Abstract: A wavelength router receives light having a plurality of spectral bands at an input port. Subsets of these spectral bands are directed to output ports. The wavelength router includes an optical train and a routing mechanism. The optical train is disposed between the input port and output ports. It provides optical paths for routing the spectral bands and includes a wave plate for rotation polarization components and a dispersive element disposed to intercept light traveling from the input port. The optical train is configured so that light encounters the dispersive element and the wave plate twice before reaching any of the output ports. The routing mechanism has at least one dynamically configurable routing element to direct a given spectral band to different output ports depending on its state. For routing elements that use an odd number of reflections, the wave plate is a quarter-wave plate. For routing elements that use an even number reflections, the wave plate is a half-wave plate.

Abstract: The utilization of an non-QOS guaranteed network is envisioned within a communication network to increase bandwidth when necessary. In this system two locations are connected by two separate communications networks one QOS guaranteed QOS guaranteed network while the other non-QOS guaranteed packet based network without QOS guarantee. A smart buffering system integrates the two networks.

Abstract: An encoding system includes an encoder that encodes uncompressed video data to form compressed video data and a decoder that decodes the compressed video data to form at least an approximation of the uncompressed video data. The video data comprises a sequence of a plurality of image frames comprising key frames and nonkey frames. In encoding a nonkey frame, reference is made to segments of a reference frame. Kinetic information, such as motion vectors, relates portions of the nonkey frame to the segments of it reference frame. The information content of the nonkey frame that is not conveyed by the segmentation, the reference frame content and the kinetic information can be encoded as residue data. Each segment's residue data, or the nonkey frame's residue data, can be encoded as coefficients of basis functions known to both the encoder and the decoder.

Abstract: Techniques for implementing vocoders in parallel digital signal processors are described. A preferred approach is implemented in conjunction with the BOPS® Manifold Array (ManArray™) processing architecture so that in an array of N parallel processing elements, N channels of voice communication are processed in parallel. Techniques for forcing vocoder processing of one data-frame to take the same number of cycles are described. Improved throughput and lower clock rates can be achieved.

Abstract: A microstructure for steering light is provided that may be stepwise controlled to provide tilt positions in two dimensions. The arrangement is two-dimensional since a tilt axis may be defined as the axis along which the base is tilted to move from one of the two tilt positions to the other. At least one additional tilt position is provided that cannot be reached from either of those two tilt positions by tilting the micromirror assembly along the tilt axis. Instead, such an additional tilt position requires that there at least be a tilt component in a direction orthogonal to the tilt axis.

Abstract: An optical cross-connect switch is provided for routing optical data signals in an optical transport network.

Abstract: A systematic approach to architecture and design of the instruction fetch mechanisms and instruction set architectures in embedded processors is described. This systematic approach allows a relaxing of certain restrictions normally imposed by a fixed-size instruction set architecture (ISA) on design and development of an embedded system. The approach also guarantees highly efficient usage of the available instruction storage which is only bounded by the actual information contents of an application or its entropy. The result of this efficiency increase is a general reduction of the storage requirements, or a compression, of the instruction segment of the original application. An additional feature of this system is the full decoupling of the ISA from the core architecture. This decoupling allows usage of a variable length encoding for any size of the ISA without impacting the physical instruction memory organization or layout and branching mechanism as well as tuning of the execution core to the application.

Abstract: Port priorities are defined on a 32-bit word, 16-bit half-word, and 8-bit byte basis to control the write enable signals to a compute register file (CRF). With a manifold array (ManArray) reconfigurable register file, it is possible to have double-word 64-bit and single word 32-bit data-type instructions mixed with other double-word, single-word, half-word, or byte data-type instructions within the same very long instruction word (VLIW). By resolving a write priority conflict on the byte, half-word, or word that is in conflict during the VLIW execution, it is possible to have partial operations complete that provide a useful function. For example, a load half-word to the half-word H0 portion of a 32-bit register R0 can have priority to complete its operation while a 64-bit shift of the register pair R0 and R1 will complete its operation on the non-conflicting half-word portions of the 64-bit register R0 and R1.

Abstract: The present invention provides improved MEMS devices and methods for use with fiber-optic communications systems. In one embodiment, an apparatus for steering light has a beam layer (160) with a reflective surface. The device uses a multi-layer electrode stack underlying the beam layer to rotate the beam layer into a desired position. Additionally, an underlying rotation and support structure provides a stable platform for the beam layer when the device is activated. In one embodiment, the underlying structure provides a multi-point landing system to maintain a generally flat beam layer upper surface when the device is activated.

Abstract: An interface source system providing at least two paths to load an instruction decode register of a coprocessor is disclosed. The interface source system includes an instruction port register, an instruction memory, an instruction decode register, and an interrupt vector table (IVT) stored in the instruction memory. The IVT stores an external instruction vector containing either a predetermined value indicating that the instruction decode register is to be loaded with contents from the instruction port register or an address of an instruction in the instruction memory. A first one of the at least two paths is used to load the instruction from the instruction memory containing the IVT if the external instruction vector contained the address of the instruction in the instruction memory. A second one of the at least two paths is used to load the instruction from the instruction port register if the external instruction vector contained the predetermined value.

Abstract: In accordance with the present invention, an improved method is provided for synchronizing a pulse stream with a data stream in an optical communications system. The improved method includes: generating an optical data signal for transmission through the optical communication system, where the data stream exhibits a duty cycle less than fifty percent and the optical data signal is formed from the pulse stream and the data stream; detecting an optical power level associated with the optical data signal; and synchronizing the pulse stream with the data stream based on the optical power level associated with the optical data signal. Specifically, the pulse stream is temporally aligned with the data stream when the average power of the optical data signal is maximized.

Abstract: General purpose flags (ACFs) are defined and encoded utilizing a hierarchical one-, two- or three-bit encoding. Each added bit provides a superset of the previous functionality. With condition combination, a sequential series of conditional branches based on complex conditions may be avoided and complex conditions can then be used for conditional execution. ACF generation and use can be specified by the programmer. By varying the number of flags affected, conditional operation parallelism can be widely varied, for example, from mono-processing to octal-processing in VLIW execution, and across an array of processing elements (PE)s. Multiple PEs can generate condition information at the same time with the programmer being able to specify a conditional execution in one processor based upon a condition generated in a different processor using the communications interface between the processing elements to transfer the conditions.

Abstract: Techniques for implementing vocoders in parallel digital signal processors are described. A preferred approach is implemented in conjunction with the BOPS® Manifold Array (ManArray™) processing architecture so that in an array of N parallel processing elements, N channels of voice communication are processed in parallel. Techniques for forcing vocoder processing of one data-frame to take the same number of cycles are described. Improved throughput and lower clock rates can be achieved.

Abstract: Methods and apparatuses are provided for protecting an interconnect line in a microelectromechanical system. The interconnect line is disposed over a substrate for conducting electrical signals, such as from a bonding pad to a mechanical component to effect movement as desired of the mechanical component. A first protective covering is disposed over a first portion of the interconnect line and a second protective covering is disposed over a second portion of the interconnect line. The first protective covering is provided in electrical communication with the substrate and the second protective covering is electrically isolated from the substrate.

Abstract: A method and system are provided for operating a transmission system having connected nodes. Channels are assigned for carrying traffic along the connections according to a multiple protection classes. Traffic may then be propagated over the connections in accordance with the assigned protection classes.

Abstract: An adaptive method is provided for applying chirp to an optical signal traversing through an optical network. The adaptive method comprises: applying chirp to an optical data signal at a transmitter in the optical network; transmitting the optical data signal through the optical network, the optical data signal having error detection data embedded therein; determining an error rate for the optical data signal at an egress point of the optical network, where the error rate is based on the error detection data embedded in the optical data signal; transmitting the error rate for the optical data signal to the transmitter; and adjusting the chirp being applied to the optical data signal at the transmitter based on the error rate for the optical data signal.

Abstract: A method is provided for seamless migration from static to agile optical networking at a network switching node in an optical transport network. The seamless method includes: providing an optical signal splitter at the input of thenetwork switching node, the signal splitter being adapted to receive an optical multiplexed signal having a plurality of data signals and at least one data signal being agile; providing an optical signal combiner at the output of the network switching node; and introducing a photonic cross-connect switch between the signal splitter and the signal combiner, where the photonic switch is operable to switch the agile data signals.

Abstract: A diffraction grating that achieves high diffraction efficiency at all polarizations for optical signals at telecommunications wavelengths is provided. The diffraction grating has a substrate and a plurality of reflective faces oriented at respective blaze angles ?b spaced along the substrate surface, with the blaze angles substantially differ from the Lit trow condition. Each reflective surface is supported by a support wall connected substantially with the substrate surface.