Abstract: In accordance with an embodiment, a method of encoding includes generating for each transform point a double difference coefficient (comprising the difference between a modeled difference coefficient and a raw difference coefficient) and encoding as an adaptive difference coefficient for each transform point either the double difference coefficient or the raw difference coefficient. Whether the double difference coefficient or the raw difference coefficient is selected to be the adaptive difference coefficient depends on which one provides more efficient coding. A method of decoding includes receiving the adaptive difference coefficients from the encoder, applying the same modeling and transform as the encoder to generate the modeled difference coefficients, generating corrective difference coefficients (from the adaptive difference coefficients and the modeled coefficients), and inverse transformation using the corrective difference coefficients.

Abstract: A microstructure for steering light is provided that may be stepwise controlled to provide tilt positions in two dimensions. The arrangement is two-dimensional since a tilt axis may be defined as the axis along which the base is tilted to move from one of the two tilt positions to the other. At least one additional tilt position is provided that cannot be reached from either of those two tilt positions by tilting the micromirror assembly along the tilt axis. Instead, such an additional tilt position requires that there at least be a tilt component in a direction orthogonal to the tilt axis.

Abstract: An optical routing apparatus and method that achieves improved optical signal reintegration is disclosed. The optical routing apparatus includes an input port, such as may be provided at the end of an optical fiber. The signal may be routed to one or more of a plurality of output ports, such as may also be provided at the end of an optical fiber, each output port being configured to receive the optical signal. The routing between the input port and the output ports is accomplished with an optical switching arrangement that may shift among multiple distinct optical configurations, each configuration being such as to direct the optical signal to one of the output ports. The ports are positioned such that the input port and at least one of the output ports lie in different parallel planes, each such plane being orthogonal to a path along which the optical signal is provided by the input port or received by one of the output ports.

Abstract: A highly parallel data processing system includes an array of n processing elements (PEs) and a controller sequence processor (SP) wherein at least one PE is combined with the controller SP to create a Dynamic Merged Processor (DP) which supports two modes of operation. In its first mode of operation, the DP acts as one of the PEs in the array and participates in the execution of single-instruction-multiple-data (SIMD) instructions. In the second mode of operation, the DP acts as the controlling element for the array of PEs and executes non-array instructions. To support these two modes of operation, the DP includes a plurality of execution units and two general-purpose register files. The execution units are “shared” in that they can execute instructions in either mode of operation. With very long instruction word (VLIW) capability, both modes of operation can be in effect on a cycle by cycle basis for every VLIW executed.

Abstract: The ManArray core indirect VLIW processor consists of an array controller sequence processor (SP) merged with a processing element (PE0) closely coupling the SP with the PE array and providing the capability to share execution units between the SP and PE0. Consequently, in the merged SP/PE0 a single set of execution units are coupled with two independent register files. To make efficient use of the SP and PE resources, the ManArray architecture specifies a bit in the instruction format, the S/P-bit, to differentiate SP instructions from PE instructions. Multiple register contexts are obtained in the ManArray processor by controlling how the array S/P-bit in the ManArray instruction format is used in conjunction with a context switch bit (CSB) for the context selection of the PE register file or the SP register file.

Abstract: A wavelength router that selectively directs spectral bands between an input port and a set of output ports. The router includes a free-space optical train disposed between the input ports and said output ports, and a routing mechanism. The free-space optical train can include air-spaced elements or can be of generally monolithic construction. The optical train includes a dispersive element such as a diffraction grating, and is configured so that the light from the input port encounters the dispersive element twice before reaching any of the output ports. The routing mechanism includes one or more routing elements and cooperates with the other elements in the optical train to provide optical paths that couple desired subsets of the spectral bands to desired output ports. The routing elements are disposed to intercept the different spectral bands after they have been spatially separated by their first encounter with the dispersive element.

Abstract: Techniques are described for decoupling fetching of an instruction stored in a main program memory from earliest execution of the instruction. An indirect execution method and program instructions to support such execution are addressed. In addition, an improved indirect deferred execution processor (DXP) VLIW architecture is described which supports a scalable array of memory centric processor elements that do not require local load and store units.

Abstract: A method and system are described which provide flexible coupling between a coprocessor and a control processor. The system includes a coprocessor and a system control bus connecting the coprocessor with the control processor. The coprocessor has two modes of access. In the first mode of access, the coprocessor retrieves an instruction stored in instruction memory and, in the second mode of access, the coprocessor retrieves an instruction from the control processor. The system control bus provides a path for loading an instruction to the coprocessor's shadow instruction register. The coprocessor, upon retrieving an entry in its instruction memory associated with the shadow instruction resigter, determines whether to load the instruction as an address in its program counter or to load the contents of the shadow instruction register into the instruction decode register.

Abstract: A microstructure is provided including a base layer underlying a first and second structural plates. Operation of the microstructure is capable of overcoming stiction. Methods of operation include providing an edge of the first structural plate in contact with a contact point. A second structural plate is deflected in a way that overcomes stiction between the first structural plate and the contact point. Such deflection can include providing a prying force to lift the first structural plate or a hammering force to disturb any stiction related forces at the contact point.

Abstract: Techniques for providing improved data distribution to and collection from multiple memories are described. Such memories are often associated with and local to processing elements (PEs) within an array processor. Improved data transfer control within a data processing system provides support for radix 2, 4 and 8 fast Fourier transform (FFT) algorithms through data reordering or bit-reversed addressing across multiple PEs, carried out concurrently with FFT computation on a digital signal processor (DSP) array by a DMA unit. Parallel data distribution and collection through forms of multicast and packet-gather operations are also supported.

Abstract: A method for dynamically compensating for signal loss and dispersion in an optical signal traversing though an optical network. The method includes providing a dynamic gain equalization filter (DGEQ) having a dynamically adjustable transfer function, and providing a first optical amplifier and a second optical amplifier interconnected by the DGEQ to form a dynamic amplifier site in the optical network. The method further includes controlling spectral power profile of the optical signal at an output of the dynamic amplifier site by dynamically adjusting a transfer function associated with the DGEQ.

Abstract: A number of methods and systems for overcoming stiction are provided. The systems include electro-mechanical systems capable of exerting a variety of forces upon areas prone to stiction. The systems can be MEMS arrays or other types of devices where stiction related forces occur. The methods include a variety of ways of causing movement in areas prone to stiction forces. Such movement can be vibrational in nature and is sufficient to overcome stiction, allowing a trapped element to be moved to a desired location.

Abstract: A number of methods and systems for overcoming stiction are provided. The systems include electromechanical systems capable of exerting a variety of forces upon areas prone to stiction. The systems can be MEMS arrays or other types of devices where stiction related forces occur. The methods include a variety of ways of causing movement in areas prone to stiction forces. Such movement can be vibrational in nature and is sufficient to overcome stiction, allowing a trapped element to be moveed to a desired location.

Abstract: An optical ring is provided for propagating optical signal pairs over wavelength connections between nodes. Each optical signal pair includes two signals at different wavelengths. At one or more of the nodes, one signal of the pair acts as a transmit signal and the other acts as a receive signal. If a failure is detected the optical signal pair is redirected over a protection path without changing the wavelengths of the transmit and receive signals. This may be achieved by reversing a propagation direction for each of the signals comprised by the redirected optical signal pair.

Abstract: Hardware and software techniques for interrupt detection and response in a scalable pipelined array processor environment are described. Utilizing these techniques, a sequential program execution model with interrupts can be maintained in a highly parallel scalable pipelined array processing containing multiple processing elements and distributed memories and register files. When an interrupt occurs, interface signals are provided to all PEs to support independent interrupt operations in each PE dependent upon the local PE instruction sequence prior to the interrupt. Processing/element exception interrupts are supported and low latency interrupt processing is also provided for embedded systems where real time signal processing is required. Further, a hierarchical interrupt structure is used allowing a generalized debug approach using debut interrupts and a dynamic debut monitor mechanism.

Abstract: A pipelined data processing unit includes an instruction sequencer and n functional units capable of executing n operations in parallel. The instruction sequencer includes a random access memory for storing very-long-instruction-words (VLIWs) used in operations involving the execution of two or more functional units in parallel. Each VLIW comprises a plurality of short-instruction-words (SIWs) where each SIW corresponds to a unique type of instruction associated with a unique functional unit. VLIWs are composed in the VLIW memory by loading and concatenating SIWs in each address, or entry. VLIWs are executed via the execute-VLIW (XV) instruction. The iVLIWs can be compressed at a VLIW memory address by use of a mask field contained within the XV1 instruction which specifies which functional units are enabled, or disabled, during the execution of the VLIW. The mask can be changed each time the XV1 instruction is executed, effectively modifying the VLIW every time it is executed.

Abstract: A hierarchical instruction set architecture (ISA) provides pluggable instruction set capability and support of array processors. The term pluggable is from the programmer's viewpoint and relates to groups of instructions that can easily be added to a processor architecture for code density and performance enhancements. One specific aspect addressed herein is the unique compacted instruction set which allows the programmer the ability to dynamically create a set of compacted instructions on a task by task basis for the primary purpose of improving control and parallel code density. These compacted instructions are parallelizable in that they are not specifically restricted to control code application but can be executed in the processing elements (PEs) in an array processor. The ManArray family of processors is designed for this dynamic compacted instruction set capability and also supports a scalable array of from one to N PEs.

Abstract: An optical routing apparatus that allows flexible and effective routing of optical signals between input and output ports is provided. The apparatus makes use of one or more linearly actuated mirrors, with different routing configurations of the optical signals resulting from different mirror positions. For each such mirror, the linear actuation is may be performed along an axis that is either parallel or perpendicular to the mirror surface.

Abstract: Low power architecture features and techniques are provided in a scalable array indirect VLIW processor. These features and techniques include power control of a reconfigurable register file, conditional power control of multi-cycle operations and indirect VLIW utilization, and power control of VLIW-based vector processing using the ManArray register file indexing mechanism. These techniques are applicable to all processing elements (PEs) and the array controller sequence processor (SP) to provide substantial power savings.

Abstract: Hardware and software techniques for interrupt detection and response in a scalable pipelined array processor environment are described. Utilizing these techniques, a sequential program execution model with interrupts can be maintained in a highly parallel scalable pipelined array processing containing multiple processing elements (PEs) and distributed memories and register files. When an interrupt occurs, interface signals are provided to all PEs to support independent interrupt operations in each PE dependent upon the local PE instruction sequence prior to the interrupt. Processing/element exception interrupts are supported and low latency interrupt processing is also provided for embedded systems where real time signal processing is required. Further, a hierarchical interrupt structure is used allowing a generalized debug approach using debug interrupts and a dynamic debuts monitor mechanism.