Abstract: An encoder system includes a disc coupled to a hub, the disc including a sensible member. The encoder system also includes a sensor operable to cooperate with the sensible member to sense an operating parameter of the disc, and a base assembly movable relative to the hub. A portion of the sensor is coupled for co-movement with the base assembly and movable between a first position in which the portion of the sensor is a first axial distance from the disc and a second position in which the portion of the sensor is a second axial distance from the disc, the second axial distance falling within a desired operating range.

Abstract: Disclosed is a semiconductor light emitting device including: a substrate; an n-type semiconductor layer giving an electron when receiving voltage; a p-type semiconductor layer giving a hole when receiving voltage; an active layer provided between the n-type semiconductor layer and the p-type semiconductor layer and including a quantum well structure to facilitate coupling between an electron and a hole; an n-type electrode including conductivity for applying voltage to the n-type semiconductor layer; a p-type electrode including conductivity for applying voltage to the p-type semiconductor layer; and am electric-current diffusion and hole injection layer provided between the p-type semiconductor layer and the p-type electrode and doped with n-type impurities and p-type impurities for diffusing an electric current and injecting a hole between the p-type electrode and the p-type semiconductor layer.

Abstract: Active compensation techniques are used for control of temperature, wavelength, and other characteristics of lasers within a laser array. The laser array includes a plurality of lasers and a plurality of dissipation elements. The dissipation elements can be interstitial to the lasers and can be implemented as non-lasing diodes. The dissipation elements are selectively activated (i.e., turned “on” to dissipate power) to adjust the temperature at the laser junctions. The change in junction temperature allows the lasers to operate at their specified wavelengths. The dissipation elements can be individually controlled and two or more bits of resolution can be provided. Active compensation can be used to adjust (i.e., to compensate) the temperature of selected lasers when one or more lasers are deselected. Active compensation can also be used to adjust (i.e., “tweak”) the wavelengths of the lasers within the laser array to be within their specified wavelengths.

Abstract: Apparatus is provided for the treatment of a medical condition, such as mucositis in patients who are undergoing cancer treatment. The apparatus has several embodiments. In each embodiment, an array of optoelectronic devices, such as light-emitting diodes (LEDs), is used to provide a uniform emission of monochromatic light while producing a minimal amount of heat. The LEDs may be cooled in several ways. The treatments are typically of a very short duration. In several embodiments, selected portions of the patient are treated using a hand-held or stationary lamp. In other embodiments, the entire gastrointestinal tract may be treated simultaneously.

Abstract: A photonic integrated circuit has a multi-wavelength laser array and an active waveguide coupler receiving outputs of the laser array. The active waveguide coupler facilitates high output power coupling of the outputs of the laser array to a single mode optical fiber.

Abstract: An IC laser array package is provided wherein standard CMOS integrated circuit (IC) processes are used for fabricating the controller for the laser array and wherein p-channel MOSFET devices are used as switches with the controller which short the anode of the selected laser in the array (connected to the drain of the p-channel MOSFET switches) to ground. In this structure, the modulating signal from the driver input can be applied to the common cathode substrate of the laser array bar in a standard package, along with a negative dc bias current provided from the negative voltage dc bias package pin through an inductor, in the same built-in bias tee manner previously used with a standard single-laser 14-pin package. Because the p-channel MOSFETs are used only as switches, their ft values are typically not a material hindrance to the circuit operation.

Abstract: The invention provides a system for sensing angular motion. The system includes a light source, a transducing member, and a modulating member having a track of translucent and opaque regions positioned between the light source and the transducing member. The transducing member includes optical receivers spaced across a width larger than or equal to three translucent and three opaque regions. The optical receivers, which may be interlaced across the transducing member, generate a plurality of output signals that form at least one output channel signal. The system may further include a second track of translucent and opaque regions and a second interlaced transducing member. The second transducing member includes a second plurality of optical receivers arranged to generate a plurality of signals that may be used to generate at least one index signal.

Abstract: Active compensation techniques are used for control of temperature, wavelength, and other characteristics of lasers within a laser array. The laser array includes a plurality of lasers and a plurality of dissipation elements. The dissipation elements can be interstitial to the lasers and can be implemented as non-lasing diodes. The dissipation elements are selectively activated (i.e., turned “on” to dissipate power) to adjust the temperature at the laser junctions. The change in junction temperature allows the lasers to operate at their specified wavelengths. The dissipation elements can be individually controlled and two or more bits of resolution can be provided. Active compensation can be used to adjust (i.e., to compensate) the temperature of selected lasers when one or more lasers are deselected. Active compensation can also be used to adjust (i.e., “tweak”) the wavelengths of the lasers within the laser array to be within their specified wavelengths.

Abstract: An IC laser array package is provided wherein standard CMOS integrated circuit (IC) processes are used for fabricating the controller for the laser array and wherein p-channel MOSFET devices are used as switches with the controller which short the anode of the selected laser in the array (connected to the drain of the p-channel MOSFET switches) to ground. In this structure, the modulating signal from the driver input can be applied to the common cathode substrate of the laser array bar in a standard package, along with a negative dc bias current provided from the negative voltage dc bias package pin through an inductor, in the same built-in bias tee manner previously used with a standard single-laser 14-pin package. Because the p-channel MOSFETs are used only as switches, their ft values are typically not a material hindrance to the circuit operation.

Abstract: Phase masks which can be used to make both linear and curved gratings of single or multiple submicron pitches, with or without any abrupt quarter-wavelength shifts (or gradually varying finer phase shifts) simultaneously on the wafer/substrate. The phase masks are made using direct write electron or ion-beam lithography of two times the required submicron pitches of linear and curved gratings on commercially available &pgr; phase-shifting material on a quartz substrate and wet or dry etching of the &pgr; phase-shifting material. The phase masks can be used in connection with making multi-wavelength laser diode chips. The laser diodes have a ridge structure with metal shoulders on either side of the ridge. The laser diode chip, with different wavelength lasers, is bonded and interfaced to a novel microwave substrate that allows for high signal-to-noise ratio and low crosstalk. The substrate is packaged in a low loss rugged housing for WDM applications.

Abstract: An apparatus and method for coupling an array of light beams extending predominantly in one direction into an output port. The light beams are rearranged into a desired shape which extends more equally along two directions than does incident array of light beams. The operation of the rearranging is wavelength insensitive. The rearranged light beams are focused onto the output port. For output ports having a small interface, the focal length of a lens focusing the rearranged light beams to the output port should be as short as possible.

Abstract: A timer circuit for providing output pulses of an adjustable duration based upon stored decode parameters. The circuit has a timer element which generates a periodic timing signal. Preferably the frequency of the periodic timing signal is also adjustable. A frequency divider is clocked by the timing signal and provides a plurality of frequency divided outputs. A decode circuit combines selected ones of the frequency divided outputs based upon decode parameters and generates a timer circuit output pulse having a duration determined by the frequency divided outputs selected by the decode parameters. The decode parameters are stored in a non-volatile data storage unit so that the timer output pulse will remain the same after power interruption.

Abstract: An apparatus and method which sequentially selects subsets of data bits read in parallel from an array of memory cells (each cell being operated as a multistate memory device) and sequentially asserts the selected subsets to a data bus. Preferably, the cells are flash memory cells. Preferably, the apparatus includes a sense amplifier circuit, a multiplexer, and circuitry operable to read a number (N) of the cells in parallel, whether the cells are operated as binary or multistate devices. The sense amplifier has N input lines and MN output lines, where M is the number of binary bits in a binary representation of the data read from each cell operated as a multistate device. The multiplexer has MN inputs (each connected to one of the output lines of the sense amplifier circuit), N outputs connected to a data bus having N-bit width, and is controllable to output selected N-bit subsets of the MN bits received at its MN inputs.

Abstract: A test mode circuit for use in a data system includes a test mode code latch for receiving a test mode code. A switch, which when turned on, couples the test mode code latch to the input so that the test mode code can be transferred from the input to the test mode code latch. A test mode command decoder is coupled to the test mode code latch for decoding the test mode code to initiate a test mode of operation in the data system. A data storage unit is coupled to the test mode command decoder for storing a data bit which corresponds to a low voltage test mode enable signal. The data bit may be modified during the test mode of operation. A low voltage test mode circuit is coupled to the data storage unit which, after first being enabled by the low voltage test mode enable signal, can be controlled to turn the switch on and off. An enable signal generation circuit couples the low voltage test mode circuit to the switch for turning the switch on and off.

Abstract: An arrangement of non-volatile memory cells, such as flash memory cells which includes erase blocks which can be separately erased and which require a reduced amount of circuit area. The erase blocks each include an array of the cells arranged in rows and columns. Each cell in a row has its control gate connected to a common word line and its drain connected to a common bit line. All of the sources of one of the erase blocks are connected together by a source line structure which includes non-metallic source lines, such as doped semiconductor lines, which run generally parallel with respect to the word line and interconnect the sources of cell located in a row. The source line structure further includes at least one metallic source line which functions to interconnect the source regions of cells located in one of the erase block cell columns.

Abstract: An apparatus determining the state of a multistate memory cell. The apparatus includes three sense amplifiers, each with an associated reference cell which produces a reference voltage for input to each of the sense amplifiers. The apparatus includes circuitry which allows the reference cell currents to be varied to produce the reference voltages or pairs of reference voltages needed to accurately determine the threshold voltage and hence state of a programmed or erased memory cell.

Abstract: An integrated memory circuit having an array of memory cells and which is operable in at least one test mode as well as in a normal operating mode, and a true V.sub.th measurement test implemented by such circuit The memory circuit includes circuitry for implementing a true V.sub.th measurement test mode in which an external voltage (or a sequence of external voltages) is applied to an external pad, and a test voltage at least substantially equal to such external voltage (or a sequence of test voltages, each at least substantially equal to one of a sequence of external voltages) is applied directly to the control gates of all or selected ones of rows of the cells (e.g., to all or selected ones of the wordlines of the array). In preferred embodiments, each memory cell is a nonvolatile memory cell such as a flash memory cell.

Abstract: A flash memory system powered by an external primary voltage source, with the system including an array of flash memory cells arranged in rows and columns, with each of the cells including a source region, a drain region, a channel region intermediate the drain and source region, a floating gate disposed over the channel region and a control gate disposed over the floating gate, with the cells located in one of the array columns having their drains connected to a common bit line and with the cells in one of the rows having their control gates connected to a common word line. The memory system includes a control circuit carrying out read, programming and erase operations. The erase operation is performed by applying a negative voltage to control gate of the cell being erased and a positive voltage to the source of the cells being erased.

Abstract: An apparatus and method for detecting an over-programming condition in a multistate memory cell. The invention is also directed to identifying the over-programmed cells and providing an alternate location at which to write the data intended for the over-programmed cell. An over-programmed state detection circuit generates an error signal when the data contained in a multistate memory cell is found to be over-programmed relative to its intended programming (threshold voltage level) state. Upon detection of an over-programmed cell, the programming operation of the memory system is modified to discontinue further programming attempts on the cell. The over-programmed state detection circuit is also used to assist in correcting for the over-programming state, permitting the programming error to be compensated for by the memory system.

Abstract: An apparatus and method for programming the memory cells of a multistate memory. The method involves the collapsing of data before transmitting to the memory cells. A controller generates optimized program pulses of high voltage to apply to the memory cells. The pulses vary in amplitude and time, depending on the state level being transitioned. Program verify is performed by reading the programmed data back into the controller where it is compared with the original value intended for programming. This compare operation modifies the data read and initial data to reflect which memory cells require further programming. The modified data is again collapsed and sent to the memory for further programming and verify cycles until a monitoring circuit within the controller detects that no further programming is required.