Abstract: A packet header preloading apparatus comprises at least a packet detector, at least a packet header buffer and at least a data dispatcher. The at least a packet detector is configured to detect an operation of a packet direct memory access controller storing at least a packet into a main memory. The at least a data dispatcher is configured to read a header of the at least a packet from the main memory and to temporarily store the header in the at least a packet header buffer.

Abstract: A method for decoding LDPC code comprises the steps of: marking non-zero sub-matrices of a parity-check matrix of an LDPC code as 1 and zero sub-matrices of the parity-check matrix as 0 to form a simplified matrix; rearranging the sequence of rows of the simplified matrix according to the dependency between these rows; and updating the LDPC code in accordance with the sequence of the rows.

Abstract: A method for forwarding packets first checks a forwarding table of a bridge to find whether the destination information for a packet is included in the forwarding table. If the information is found, this packet is forwarded to the destination through a physical layer directly without passing through the bridge. This method improves the efficiency of the frame aggregation of an AP (Access Point) and enhances the throughput in a WLAN (Wireless Local Area Network).

Abstract: A method for decomposing a barrel shifter decomposes N, the number of digits of input word, into N1 to Nm, and utilizes m layers of shifter circuit layer, which are composed of a plurality of barrel shifters, such that each barrel shifter performs a shifting procedure to obtain the desired output word.

Abstract: A method for calibrating an analog circuit component comprises the steps of: generating a first signal with a baseband frequency; generating a second signal by processing the first signal via the analog component to be calibrated; generating a third signal by processing the second signal via a power amplifier, wherein the power amplifier operates in a nonlinear region; generating a fourth signal by processing the third signal via a low-pass filter; and defining the adjustment for the In-phase-Quadrature-phase imbalance (IQ imbalance) of the analog component and then re-executing the step of generating the first signal, if the fourth signal shows an IQ imbalance mismatch.

Abstract: Varying embodiments of the present invention describe a closed loop system for processing the beamforming information, qualifying the expected performance, activating and deactivating the beamforming system. A first embodiment is a method for closed loop beamforming in a wireless communication system, the system comprising a transmitter and a receiver, the method comprising initiating beamforming on a communication channel between the transmitter and the receiver, monitoring the communication channel, periodically determining a condition of the communication channel and controlling beamforming based on the condition of the communication channel.

Abstract: Phase-locked loop charge pump driven by low voltage input. In one aspect, a phase-locked loop circuit includes a phase frequency detector operating at a low voltage and providing low-voltage sourcing control signals and low-voltage sinking control signals at the low voltage. A charge pump operates at a high voltage and includes a sourcing control circuit coupled to the low-voltage sourcing control signals and selectively causing the charge pump to source the sourcing current to an output of the charge pump based on the low-voltage sourcing control signals. The charge pump also includes a sinking control circuit that receives the low-voltage sinking control signals and selectively causes the charge pump to sink the sinking current from the output of the charge pump based on the low-voltage sinking control signals.

Abstract: A multi input multi output (MIMO) receiver is disclosed for transmitting and receiving packets having a preamble format of a packet of information and having a short training sequence (STS), a long training sequence (LTS) and signal (SIG) for training receivers, in accordance with an embodiment of the present invention. The packets having a preamble format for allowing data to be piggy-backed, e.g. transmitted and received using the physical layer rather than the transport layer of networking layers.

Abstract: A method for selecting a modulation and coding scheme (MCS) applied to a multiple-antenna system. The method calculates the throughout of a plurality of MCSs based on the signal to noise ratio of the multiple-antenna system and selects a MCS from the plurality of MCSs accordingly.

Abstract: A rate adaptation method comprises the steps of: updating the probability density function of the SNR of a transmitted signal according to the receiving status of the transmitted signal and the probability density function before update; and updating the transmission rate of the transmitted signal according the updated probability density function.

Abstract: A method for radio frequency transmitting and receiving beamforming using both GPS guidance and wireless access points is disclosed. The method comprises providing a wireless networking device with preloaded wireless access point locations; calculating a relative vector to an access point based upon at least one of the preloaded wireless access point locations; steering a transmitted beam with a sounding packet to the access point; calculating a channel condition by the access point; and sending a packet by the access point to the wireless networking device to establish a connection.

Abstract: A method for writing a memory of a block interleaver determines in a bit-wise manner whether to write data into the memory. A method for reading a memory of a block interleaver combines two adjacent columns of the memory into a temporary column and reads data from the temporary column.

Abstract: An RF front-end architecture is operated in either a transmitting or a receiving mode. The RF front-end architecture comprises an antenna, an impedance match network, a balun and a transceiver chip. The transceiver chip comprises first and second transmit/receive (TR) switches, a transmitter, and a receiver. Because two TR switches are integrated into the chip, the printed circuit board area, BOM cost and pin count of the transceiver chip can be greatly reduced.

Abstract: Phase-locked loop charge pump driven by low voltage input. In one aspect, a charge pump for a phase-locked loop circuit includes a sourcing current transistor providing a sourcing current, wherein the sourcing current transistor is coupled to a high-voltage operating voltage supply. A sourcing control circuit uses low-voltage sourcing control signals to selectively cause the charge pump to source the sourcing current to an output of the charge pump, and a sinking control circuit uses low-voltage sinking control signals to selectively cause the charge pump to sink the sinking current from the output.

Abstract: The present invention provides a planar antenna, including an inverted F-shaped antenna module having a first resonance unit, a second resonance unit and a linear feed-in unit, and a linear ground unit, wherein the linear ground unit is perpendicularly connected to the first and second resonance units to form a rectangular resonance cavity, the two resonance units have the same signal feed-in end but different widths, thereby resulting in different route lengths for generation of two sets of signals with different frequency responses. Further, by adjusting frequency bands of the two sets of signals with optimal responses to achieve a signal coupling resonance effect, signals with frequencies matching the resonant frequencies achieve high gain and high radiation efficiency and signals with frequencies different from the resonant frequencies are suppressed and cannot be efficiently radiated.

Abstract: A balanced patched inverse F antenna comprises a radiation conductor and a balun circuit. The radiation conductor includes a main body, a first branch and a second branch. The balun circuit includes an unbalanced port, a balanced port, and first, second, third and fourth components, with the first, second, third and fourth components being serially connected. A feeding input of the unbalanced port is connected to the second and third components, a grounding wire of the unbalanced port is connected to the first and fourth components, an inverting terminal of the balanced port is connected to the first and second components, a non-inverting terminal of the balanced port is connected to the third and fourth components, and the inverting and non-inverting terminals are respectively connected to the first and second branches.

Abstract: A device and method for DC offset cancellation device are disclosed. The method includes keeping a high pass module at off state, converting an analog radio frequency signal to a digital baseband signal by a direct down conversion receiving module, detecting a DC offset value during the conversion by an offset compensation module so as to provide an offset compensation signal corresponding to the DC offset value to the direct down conversion receiving module, and determining whether a control condition is reached by a control module so as to timely switch on the high pass module for canceling the residual DC offset in the direct down conversion receiving module. In the present invention, the offset compensation module provides preliminary offset compensation signals and then the high pass module accurately cancels residual DC offset, thereby significantly reducing the reaction time for DC offset cancellation.

Abstract: The present invention relates generally to the level shifter circuits and more specifically to improved level shifter circuits providing for reduced leakage current and reduced power consumption. In one or more implementations, a method, apparatus and computer program product for level shifting input voltages by minimizing current leakage of a circuit coupled with an improved level shifting circuit is provided for. In one implementation the method includes providing a low voltage domain of the circuit, and providing for turning off the transistor if the low voltage domain of the circuit is not stable, and turning on the transistor if the low voltage domain of the circuit is stable.

Abstract: A method and system for detecting packets of different formats in a receiver is disclosed. The method and system include initializing the receiver to be in a legacy mode; and receiving at least one data symbol by the receiver. The method and system include detecting if there is a high throughput (HT) signal field within a data packet and determining the format of the data packet based upon the detection of a HT signal field.

Abstract: A DMA controlling method comprises the steps of: building a linking table, wherein the linking table records the status of each memory block and of a pointer pointing to a next memory block; activating a first memory block; receiving an interrupt signal and linking to a next associated memory block after the first memory block finishes a data transfer; activating the next associated block; and updating the linking table to release the first memory block for reuse.