Abstract: The embodiments herein are directed to technologies for crosstalk cancellation structures. One semiconductor package includes conductive metal layers separated by insulating layers, the conductive metal layers for routing signals between external package terminals and pads on an integrated circuit device. Signal lines formed in the conductive metal layers have electrode structure (capacitor electrode-like structures) formed for at least adjacent signaling lines of the package terminals. Two of the electrode structures from the adjacent signaling lines are formed opposite each other on different metal layers.

Abstract: A system includes a memory controller and a memory device having a command interface, refresh circuitry, control logic, and a plurality of memory banks, each with a plurality of rows of memory cells. The command interface is operable to receive a refresh command from a memory controller and the refresh circuitry is configured to perform one or more refresh operations to refresh data stored in at least one bank of the plurality of memory banks during a refresh time interval in response to the refresh command from the memory controller. The control logic is to configure the command interface to enter a calibration mode during the refresh time interval, and the command interface is configured to perform a calibration operation in the calibration mode during the refresh time interval.

Abstract: Bandwidth for information transfers between devices is dynamically changed to accommodate transitions between power modes employed in a system. The bandwidth is changed by selectively enabling and disabling individual control links and data links that carry the information. During a highest bandwidth mode for the system, all of the data and control links are enabled to provide maximum information throughout. During one or more lower bandwidth modes for the system, at least one data link and/or at least one control link is disabled to reduce the power consumption of the devices. At least one data link and at least one control link remain enabled during each low bandwidth mode. For these links, the same signaling rate is used for both bandwidth modes to reduce latency that would otherwise be caused by changing signaling rates. Also, calibration information is generated for disabled links so that these links may be quickly brought back into service.

Abstract: The embodiments are directed to technologies for variable pitch vertical interconnect design for scalable escape routing in semiconductor devices. One semiconductor device includes a circuit die, and an array of circuit die interconnects located on the circuit die. The array includes a first triangular octant of interconnects that are organized in rows and columns, each column incrementing its number of interconnects from a first side of the first triangular octant to a second side of the first triangular octant. A pitch size between the columns increases in a first repeating pattern from the first side to the second side.

Abstract: In a memory component having a command/address interface, timing interface and data interface, the command/address interface receives a first command/address value from a control component during a first interval and a second command/address value from the control component during a second interval. The timing interface receives a data strobe from the control component during the first interval and a data clock from the control component during the second interval, the data strobe departing from a parked voltage level to commence toggling at a time corresponding to reception of the first command/address value, and the data clock toggling throughout the second interval regardless of second command/address value reception-time. The data interface samples first write data corresponding to the first command/address value at times indicated by toggling of the data strobe, and samples second write data corresponding to the second command/address value at times indicated by toggling of the data clock.

Abstract: The disclosed embodiments relate to a memory system that generates a multiplied timing signal from a reference timing signal. During operation, the system receives a reference timing signal. Next, the system produces a multiplied timing signal from the reference timing signal by generating a burst comprising multiple timing events for each timing event in the reference timing signal, wherein consecutive timing events in each burst of timing events are separated by a bit time. Then, as the reference clock frequency changes, the interval between bursts of timing events changes while the bit time remains substantially constant.

Abstract: The memory banks of a memory device are arranged and operated in groups and the groups are further arranged and operated as clusters of these groups. Successive accesses to banks that are within different bank group clusters may be issued at a first time interval. Successive accesses to banks that are within different bank groups within the same cluster can be issued no faster than a second time interval. And, successive accesses to banks that are within the same bank group may be issued no faster than a third time interval. The memory banks of a memory device may have multiple rows open at the same time. The rows that can be open at the same time is determined by the rows that are already open. These memory banks are also arranged and operated in groups that have three different minimum time intervals.

Abstract: First data is read out of a core storage array of a memory component over a first time interval constrained by data output bandwidth of the core storage array. After read out from the core storage array, the first data is output from the memory component over a second time interval that is shorter than the first time interval and that corresponds to a data transfer bandwidth greater than the data output bandwidth of the core storage array.

Abstract: A dynamic random access memory (DRAM) comprises a plurality of primary data storage elements, a plurality of redundant data storage elements, and circuitry to receive a first register setting command and initiate a repair mode in the DRAM in response to the first register setting command. The circuitry is further to receive an activation command, repair a malfunctioning row address in the DRAM, receive a precharge command, receive a second register setting command, terminate the repair mode in the DRAM in response to the second register setting command, receive a memory access request for data stored at the malfunctioning row address, and redirect the memory access request to a corresponding row address in the plurality of redundant data storage elements.

Abstract: A structure for delivering power is described. In some embodiments, the structure can include conductors disposed on two or more layers. Specifically, the structure can include a first set of interdigitated conductors disposed on a first layer and oriented substantially along an expected direction of current flow. At least one conductor in the first set of interdigitated conductors may be maintained at a first voltage, and at least one conductor in the first set of interdigitated conductors may be maintained at a second voltage, wherein the second voltage is different from the first voltage. The structure may further include a conducting structure disposed on a second layer, wherein the second layer is different from the first layer, and wherein at least one conductor in the conducting structure is maintained at the first voltage.

Abstract: An memory component includes a memory bank and a command interface to receive a read-modify-write command, having an associated read address indicating a location in the memory bank and to either access read data from the location in the memory bank indicated by the read address after an adjustable delay period transpires from a time at which the read-modify-write command was received or to overlap multiple read-modify-write commands. The memory component further includes a data interface to receive write data associated with the read-modify-write command and an error correction circuit to merge the received write data with the read data to form a merged data and write the merged data to the location in the memory bank indicated by the read address.

Abstract: Described are integrated-circuit die with differential receivers, the inputs of which are coupled to external signal pads. Termination legs coupled to the signal pads support multiple termination topologies. These termination legs can support adjustable impedances, capacitances, or both, which may be controlled using an integrated memory.

Abstract: In a data transmission system, one or more signal supply voltages for generating the signaling voltage of a signal to be transmitted are generated in a first circuit and forwarded from the first circuit to a second circuit. The second circuit may use the forwarded signal supply voltages to generate another signal to be transmitted back from the second circuit to the first circuit, thereby obviating the need to generate signal supply voltages separately in the second circuit. The first circuit may also adjust the signal supply voltages based on the signal transmitted back from the second circuit to the first circuit. The data transmission system may employ a single-ended signaling system in which the signaling voltage is referenced to a reference voltage that is a power supply voltage such as ground, shared by the first circuit and the second circuit.

Abstract: This application is directed to a stacked semiconductor device assembly including a plurality of identical stacked integrated circuit (IC) devices. Each IC device further includes a master interface, a channel master circuit, a slave interface, a channel slave circuit, a memory core, and a modal pad configured to receive a selection signal for the IC device to communicate data using one of its channel master circuit or its channel slave circuit. In some implementations, the IC devices include a first IC device and one or more second IC devices. In accordance with the selection signal, the first IC device is configured to communicate read/write data via the channel master circuit of the first IC device, and each of the one or more second IC devices is configured to communicate respective read/write data via the channel slave circuit of the respective second IC device.

Abstract: Memory devices and a memory controller that controls such memory devices. Multiple memory devices receive commands and addresses on a command/address (C/A) bus that is relayed point-to-point by each memory device. Data is received and sent from these devices to/from a memory controller in a point-to-point configuration by adjusting the width of each individual data bus coupled between the individual memory devices and the memory controller. Along with the C/A bus are clock signals that are regenerated by each memory device and relayed. The memory controller and memory devices may be packaged on a single substrate using package-on-package technology. Using package-on-package technology allows the relayed C/A signals to connect from memory device to memory device using wire bonding. Wirebond connections provide a short, high-performance signaling environment for the chip-to-chip relaying of the C/A signals and clocks from one memory device to the next in the daisy-chain.

Abstract: A cache memory includes cache lines to store information. The stored information is associated with physical addresses that include first, second, and third distinct portions. The cache lines are indexed by the second portions of respective physical addresses associated with the stored information. The cache memory also includes one or more tables, each of which includes respective table entries that are indexed by the first portions of the respective physical addresses. The respective table entries in each of the one or more tables are to store indications of the second portions of respective physical addresses associated with the stored information.

Abstract: A memory module is disclosed. The memory module includes a substrate, and respective first, second and third memory devices. The first memory device is of a first type disposed on the substrate and has addressable storage locations. The second memory device is also of the first type, and includes storage cells dedicated to store failure address information associated with defective storage locations in the first memory device. The third memory device is of the first type and includes storage cells dedicated to substitute as storage locations for the defective storage locations.

Abstract: The dynamic memory array of a DRAM device is operated using at least two voltages. The first voltage, which is used to power the sense amplifiers during sense (i.e., read) operations and most other column operations (e.g., precharge, activate, write), is the operating (i.e., switching) voltage of a majority of the digital logic circuitry of the DRAM device. The second voltage, which determines the voltage written to the capacitor of the DRAM cells (i.e., bitline voltage) is greater than the operating (i.e., switching) voltage of a majority of the digital logic circuitry of the DRAM device. The digital logic circuitry is operated using a supply voltage that is lower than the voltage written to the capacitors of the DRAM array. This allows lower voltage swing digital logic to be used for a majority of the logic on the DRAM device while writing a larger voltage to the DRAM cells.

Abstract: A memory system includes dynamic random-access memory (DRAM) components that include interconnected and redundant component data interfaces. The redundant interfaces facilitate memory interconnect topologies that accommodate considerably more DRAM components per memory channel than do traditional memory systems, and thus offer considerably more memory capacity per channel, without concomitant reductions in signaling speeds. The memory components can be configured to route data around defective data connections to maintain full capacity and continue to support memory transactions.

Abstract: A memory module includes cache of relatively fast and durable dynamic, random-access memory (DRAM) in service of a larger amount of relatively slow and wear-sensitive non-volatile memory. Local controller manages communication between the DRAM cache and non-volatile memory to accommodate disparate access granularities, reduce the requisite number of memory transactions, and minimize the flow of data external to nonvolatile memory components.