Abstract: A system for use with a multi-phase clock generator is disclosed. It should also be understood that the multiphase clock generator can be a phase lock loop (PLL), delay lock loop (DLL), or any other circuit capable of providing a multiphase clock. The system comprises at least two phase detectors coupled to the multi-phase clock generator for receiving component clock signals of the multi-phase clock generator, wherein at least some of the component clock signals are offset from each other in phase. Each of the phase detectors detects phase differences between pairs of component clock signals. The system includes a summer coupled to the at least two phase detectors for measuring the phase differences between the at least two phase detectors. The system includes at least one variable delay element for receiving the measured phase difference and for providing a delay which is proportional to an output value of the summer. The delay is used to reduce the phase differences.

Abstract: A differential amplifier with reduced noise sensitivity enables the bus to operate more efficiently at higher data rates. The amplifier includes an input stage with a pair of adjustable resistive loads that alter the gain of the input stage. A differential output stage receives the output of the input stage and produces a pair of complementary output signals. These output signals are fed back to the adjustable resistive loads so that the gain of the input stage depends upon the levels of the output signals. The feedback is positive, so the voltage transfer characteristic of the inventive amplifier has different input thresholds for positive- and negative-going voltage signals.

Abstract: A method of controlling a synchronous memory device comprising issuing a write request to the memory device, wherein in response to the write request, the memory device samples first and second portions of data. The first portion of data is provided to the memory device synchronously with respect to a rising edge transition of an external clock signal. A second portion of data is provided to the memory device synchronously with respect to a falling edge transition of the external clock signal. A memory controller for controlling a synchronous memory device comprises output driver circuitry to output data. The output driver circuitry outputs a first portion of data in response to a rising edge transition of the first external clock signal. In addition, the output driver circuitry outputs a second portion of data in response to a falling edge transition of the first external clock signal.