Patents Assigned to Rambus Inc.
  • Patent number: 10708036
    Abstract: An integrated circuit receiver is disclosed comprising a data receiving circuit responsive to a timing signal to detect a data signal and an edge receiving circuit responsive to the timing signal to detect a transition of the data signal. One of the data or edge receiving circuits comprises an integrating receiver circuit while the other of the data or edge sampling circuits comprises a sampling receiver circuit.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: July 7, 2020
    Assignee: Rambus Inc.
    Inventor: Jared L. Zerbe
  • Patent number: 10705989
    Abstract: The described embodiments provide a system for controlling an integrated circuit memory device by a memory controller. During operation, the system sends a memory-access request from the memory controller to the memory device using a first link. After sending the memory-access request, the memory controller sends to the memory device a command that specifies performing a timing-calibration operation for a second link. The system subsequently transfers data associated with the memory-access request using the second link, wherein the timing-calibration operation occurs between sending the memory-access request and transferring the data associated with the memory-access request.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: July 7, 2020
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Holden Jessup
  • Patent number: 10706913
    Abstract: A memory stack comprises at least two memory components. The memory components have a first data link interface and are to transmit signals on a data link coupled to the first data link interface at a first voltage level. A buffer component has a second data link interface coupled to the data link. The buffer component is to receive signals on the second data link interface at the first voltage level. A level shifting latch produces a second voltage level in response to receiving the signals at the second data link interface, where the second voltage level is higher than the first voltage level.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: July 7, 2020
    Assignee: RAMBUS INC.
    Inventors: Frederick A. Ware, John Eric Linstadt, Thomas Vogelsang
  • Patent number: 10705990
    Abstract: A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal. The second clock signal times communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank. The timing circuit is configured to adjust a phase of the first clock signal, when the memory controller is communicating with the second memory device, based on calibration data associated with the second memory device and timing adjustment data associated with feedback from at least the first memory device.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: July 7, 2020
    Assignee: RAMBUS INC.
    Inventors: Jared L. Zerbe, Ian P. Shaeffer, John Eble
  • Patent number: 10706910
    Abstract: A memory controller component includes transmit circuitry and adjusting circuitry. The transmit circuitry transmits a clock signal and write data to a DRAM, the write data to be sampled by the DRAM using a timing signal. The adjusting circuitry adjusts transmit timing of the write data and of the timing signal such that an edge transition of the timing signal is aligned with an edge transition of the clock signal at the DRAM.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: July 7, 2020
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Ely K. Tsern, Richard E. Perego, Craig E. Hampel
  • Patent number: 10707885
    Abstract: A receiver includes a variable resolution analog-to-digital converter (ADC) and variable resolution processing logic/circuitry. The processing logic may use feed-forward equalization (FFE) techniques to process the outputs from the ADC. When receiving data from a channel having low attenuation, distortion, and/or noise, the ADC and processing logic may be configured to sample and process the received signal using fewer bits, and therefore less logic, than when configured to receiving data from a channel having a higher attenuation, distortion, and/or noise. Thus, the number of (valid) bits output by the ADC, and subsequently processed (e.g., for FFE equalization) can be reduced when a receiver of this type is coupled to a low loss channel. These reductions can reduce power consumption when compared to operating the receiver using the full (i.e., maximum) number of bits the ADC and processing logic is capable of processing.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: July 7, 2020
    Assignee: Rambus Inc.
    Inventors: Masum Hossain, Kenneth C. Dyer, Nhat Nguyen, Shankar Tangirala
  • Patent number: 10705988
    Abstract: A method of transferring data between a memory controller and at least one memory module via a primary data bus having a primary data bus width is disclosed. The method includes accessing a first one of a memory device group via a corresponding data bus path in response to a threaded memory request from the memory controller. The accessing results in data groups collectively forming a first data thread transferred across a corresponding secondary data bus path. Transfer of the first data thread across the primary data bus width is carried out over a first time interval, while using less than the primary data transfer continuous throughput during that first time interval. During the first time interval, at least one data group from a second data thread is transferred on the primary data bus.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: July 7, 2020
    Assignee: Rambus Inc.
    Inventors: Hongzhong Zheng, Frederick A Ware
  • Patent number: 10705912
    Abstract: Data and error correction information may involve accessing multiple data channels (e.g., 8) and one error detection and correction channel concurrently. This technique requires a total of N+1 row requests for each access, where N is the number of data channels (e.g., 8 data row accesses and 1 error detection and correction row access equals 9 row accesses.) A single (or at least less than N) data channel row may be accessed concurrently with a single error detection and correction row. This reduces the number of row requests to two (2)—one for the data and one for the error detection and correction information. Because, row requests consume power, reducing the number of row requests is more power efficient.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: July 7, 2020
    Assignee: Rambus Inc.
    Inventors: Michael Miller, Stephen Magee, John Eric Linstadt
  • Patent number: 10700671
    Abstract: An integrated circuit includes a delay circuit and first and second interface circuits. The delay circuit delays a first timing signal by an internal delay to generate an internal timing signal. The first interface circuit communicates data to an external device in response to the internal timing signal. The second interface circuit transmits an external timing signal for capturing the data in the external device. An external delay is added to the external timing signal in the external device to generate a delayed external timing signal. The delay circuit sets the internal delay based on a comparison between the delayed external timing signal and a calibration signal transmitted by the first interface circuit.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: June 30, 2020
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Ely Tsern, Brian S. Leibowitz, Jared Zerbe
  • Patent number: 10699769
    Abstract: A memory controller receives data and phase-providing signals from a memory device. The phase-providing signal is not a clock signal, but is used by the memory controller to phase align a local data-sampling signal with the incoming data. The memory controller samples the data signal with the data-sampling signal. The memory controller can perform maintenance operations to update the phase relationship between the phase-providing and data-sampling signals.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: June 30, 2020
    Assignee: Rambus Inc.
    Inventors: Scott C. Best, Richard E. Warmke, David B. Roberts, Frank Lambrecht
  • Patent number: 10698464
    Abstract: A multi-element device includes a plurality of memory elements, each of which includes a memory array, access circuitry to control access to the memory array, and power control circuitry. The power control circuitry, which includes one or more control registers for storing first and second control values, controls distribution of power to the access circuitry in accordance with the first control value, and controls distribution of power to the memory array in accordance with the second control value. Each memory element also includes sideband circuitry for enabling a host system to set at least the first control value and the second control value in the one or more control registers.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: June 30, 2020
    Assignee: RAMBUS INC.
    Inventors: Deborah Lindsey Dressler, Julia Kelly Cline, Wayne Frederick Ellis
  • Patent number: 10691860
    Abstract: The camouflage technique described herein introduces programmed configuration inputs to Micro Netlists, creating Programmable Micro Netlists (PMNLs). PMNLs are a group of camouflaged and non-camouflaged cells that may be configured to perform one of several possible logic functions. They retain all the protective properties of non-programmable MNLs, but also allow for secure post-manufacture configuration of their aggregate logic function.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: June 23, 2020
    Assignee: RAMBUS INC.
    Inventors: Lap Wai Chow, Bryan J. Wang, James P. Baukus, Ronald P. Cocchi
  • Patent number: 10684823
    Abstract: A memory module includes at least two memory devices. Each of the memory devices perform verify operations after attempted writes to their respective memory cores. When a write is unsuccessful, each memory device stores information about the unsuccessful write in an internal write retry buffer. The write operations may have only been unsuccessful for one memory device and not any other memory devices on the memory module. When the memory module is instructed, both memory devices on the memory module can retry the unsuccessful memory write operations concurrently. Both devices can retry these write operations concurrently even though the unsuccessful memory write operations were to different addresses.
    Type: Grant
    Filed: June 9, 2017
    Date of Patent: June 16, 2020
    Assignee: Rambus Inc.
    Inventors: Hongzhong Zheng, Brent Haukness
  • Patent number: 10686632
    Abstract: A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: June 16, 2020
    Assignee: Rambus Inc.
    Inventors: Jared L. Zerbe, Fariborz Assaderaghi, Brian S. Leibowitz, Hae-Chang Lee, Jihong Ren, Qi Lin
  • Patent number: 10680612
    Abstract: Local on-die termination controllers for effecting termination of a high-speed signaling links simultaneously engage on-die termination structures within multiple integrated-circuit memory devices disposed on the same memory module, and/or within the same integrated-circuit package, and coupled to the high-speed signaling link. A termination control bus is coupled to memory devices on a module, and provides for peer-to-peer communication of termination control signals.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: June 9, 2020
    Assignee: Rambus Inc.
    Inventor: Ian Shaeffer
  • Patent number: 10678719
    Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, a memory module includes a pin interface for coupling to a bus. The bus has a first width. The module includes at least one storage class memory (SCM) component and at least one DRAM component. The memory module operates in a first mode that utilizes all of the first width, and in a second mode that utilizes less than all of the first width.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: June 9, 2020
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Kenneth L. Wright, John Eric Linstadt, Craig Hampel
  • Patent number: 10678459
    Abstract: Described are memory modules that include address-buffer components and data-buffer components that together support wide- and narrow-data modes. The address-buffer component manages communication between a memory controller and two sets of memory components. In the wide-data mode, the address-buffer enables memory components in each set and instructs the data-buffer components to communicate full-width read and write data by combining data from or to from both sets for each memory access. In the narrow-data mode, the address-buffer enables memory components in just one of the two sets and instructs the data-buffer components to half-width read and write data with one set per memory access.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: June 9, 2020
    Assignee: Rambus Inc.
    Inventors: Suresh Rajan, Abhijit M. Abhyankar, Ravindranath Kollipara, David A. Secker
  • Patent number: 10674098
    Abstract: An imaging system has an imager comprising a plurality of jots. A readout circuit is in electrical communication with the imager. The readout circuit can be configured to facilitate the formation of an image by defining neighborhoods of the jots, wherein a local density of exposed jots within a neighborhood is used to generate a digital value for a pixel of the image.
    Type: Grant
    Filed: December 26, 2016
    Date of Patent: June 2, 2020
    Assignee: Rambus Inc.
    Inventor: Eric R. Fossum
  • Patent number: 10673582
    Abstract: A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: June 2, 2020
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Richard E. Perego, Craig E. Hampel
  • Patent number: 10671561
    Abstract: An integrated circuit device is disclosed including core circuitry and interface circuitry. The core circuitry outputs in parallel a set of data bits, while the interface circuitry couples to the core circuitry. The interface circuitry receives in parallel a first number of data bits among the set of data bits from the core circuitry and outputs in parallel a second number of data bits. The ratio of the first number to the second number is a non-power-of-2 value.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: June 2, 2020
    Assignee: Rambus Inc.
    Inventor: Frederick A Ware