Patents Assigned to Rambus Inc.
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Patent number: 12050513Abstract: A memory system employs an addressing scheme to logically divide rows of memory cells into separate contiguous regions, one for data storage and another for error detection and correction (EDC) codes corresponding to that data. Data and corresponding EDC codes are stored in the same row of the same bank. Accessing data and corresponding EDC code in the same row of the same bank advantageously saves power and avoids bank conflicts. The addressing scheme partitions the memory without requiring the requesting processor to have an understanding of the memory partition.Type: GrantFiled: April 25, 2023Date of Patent: July 30, 2024Assignee: Rambus Inc.Inventors: Frederick A. Ware, John E. Linstadt, Liji Gopalakrishnan
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Patent number: 12050787Abstract: The present invention is directed to computer storage systems and methods thereof. In an embodiment, a memory system comprises a controller module, a nonvolatile memory, and a volatile memory. The controller module operates according to a command and operation table. The command and operation table can be updated to change the way controller module operates. When the command and operation table is updated, the updated table is stored at a predefined location of the nonvolatile memory. There are other embodiments as well.Type: GrantFiled: February 10, 2022Date of Patent: July 30, 2024Assignee: Rambus Inc.Inventors: Shih-ho Wu, Christopher Haywood
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Patent number: 12040035Abstract: A buffer circuit is disclosed. The buffer circuit includes a command address (C/A) interface to receive an incoming activate (ACT) command and an incoming column address strobe (CAS) command. A first match circuit includes first storage to store failure row address information associated with the memory, and first compare logic. The first compare logic is responsive to the ACT command, to compare incoming row address information to the stored failure row address information. A second match circuit includes second storage to store failure column address information associated with the memory, and second compare logic. The second compare logic is responsive to the CAS command, to compare the incoming column address information to the stored failure column address information. Gating logic maintains a state of a matching row address identified by the first compare logic during the comparison carried out by the second compare logic.Type: GrantFiled: August 11, 2023Date of Patent: July 16, 2024Assignee: Rambus Inc.Inventors: Scott C. Best, John Eric Linstadt, Paul William Roukema
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Patent number: 12033683Abstract: A power-management integrated circuit (PMIC) is installed on a memory module to optimize power use among a collection of memory devices. The PMIC includes external power-supply nodes that receive relatively high and low supply voltages. Depending on availability, the PMIC uses one or both of these supply voltages to generate a managed supply voltage for powering the memory devices. The PMIC selects between operational modes for improved efficiency in dependence upon the availability of one or both externally provided supply voltages.Type: GrantFiled: April 20, 2022Date of Patent: July 9, 2024Assignee: Rambus Inc.Inventors: Panduka Wijetunga, Aws Shallal, Joey M. Esteves
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Patent number: 12032845Abstract: A compute system includes an execution unit (e.g. of a CPU) with a memory controller providing access to a hybrid physical memory. The physical memory is “hybrid” in that it combines a cache of relatively fast, durable, and expensive memory (e.g. DRAM) with a larger amount of relatively slow, wear-sensitive, and inexpensive memory (e.g. flash). A hybrid controller component services memory commands from the memory controller component and additionally manages cache fetch and evict operations that keep the cache populated with instructions and data that have a high degree of locality of reference. The memory controller alerts the hybrid controller of available access slots to the cache so that the hybrid controller can use the available access slots for cache fetch and evict operations with minimal interference to the memory controller.Type: GrantFiled: October 19, 2021Date of Patent: July 9, 2024Assignee: Rambus Inc.Inventors: Frederick A. Ware, John Eric Linstadt
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Patent number: 12032508Abstract: The timing of the synchronous interface is controlled by a clock signal driven by a controller. The clock is toggled in order to send a command to a memory device via the interface. If there are no additional commands to be sent via the interface, the controller suspends the clock signal. When the memory device is ready, the memory device drives a signal back to the controller. The timing of this signal is not dependent upon the clock signal. Receipt of this signal by the controller indicates that the memory device is ready and the clock signal should be resumed so that a status of the command can be returned via the interface, or another command issued via the interface.Type: GrantFiled: May 8, 2023Date of Patent: July 9, 2024Assignee: Rambus Inc.Inventor: Yuanlong Wang
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Patent number: 12026038Abstract: A memory system includes a link having at least one signal line and a controller. The controller includes at least one transmitter coupled to the link to transmit first data, and a first error protection generator coupled to the transmitter. The first error protection generator dynamically adds an error detection code to at least a portion of the first data. At least one receiver is coupled to the link to receive second data. A first error detection logic determines if the second data received by the controller contains at least one error and, if an error is detected, asserts a first error condition. The system includes a memory device having at least one memory device transmitter coupled to the link to transmit the second data. A second error protection generator coupled to the memory device transmitter dynamically adds an error detection code to at least a portion of the second data.Type: GrantFiled: August 14, 2023Date of Patent: July 2, 2024Assignee: Rambus Inc.Inventors: Ely K. Tsern, Mark A. Horowitz, Frederick A. Ware
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Patent number: 12026104Abstract: Space in a memory is allocated based on the highest used precision. When the maximum used precision is not being used, the bits required for that particular precision level (e.g., floating point format) are transferred between the processor and the memory while the rest are not. A given floating point number is distributed over non-contiguous addresses. Each portion of the given floating point number is located at the same offset within the access units, groups, and/or memory arrays. This allows a sequencer in the memory device to successively access a precision dependent number of access units, groups, and/or memory arrays without receiving additional requests over the memory channel.Type: GrantFiled: March 19, 2020Date of Patent: July 2, 2024Assignee: Rambus Inc.Inventors: Thomas Vogelsang, Craig E. Hampel
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Patent number: 12027197Abstract: A memory controller integrated circuit includes a clock signal generator circuit configured to generate a plurality of strobe signals. The memory controller integrated circuit further includes a memory interface circuit coupled to the clock signal generator circuit, the memory interface circuit configured to transmit the plurality of strobe signals to a memory module, wherein each of the plurality of strobe signals is offset with respect to an adjacent strobe signal, and transmit a plurality of data signals to the memory module, wherein a first subset of the plurality of data signals comprises a first nibble and is phase aligned with a first strobe signal of the plurality of strobe signals, and wherein a second subset of the plurality of data signals comprises a second nibble and is phase aligned with a second strobe signal of the plurality of strobe signals.Type: GrantFiled: December 11, 2019Date of Patent: July 2, 2024Assignee: Rambus Inc.Inventors: Shahram Nikoukary, Jonghyun Cho, Anand Jai, Pradeep Batra, Lei Luo
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Publication number: 20240215149Abstract: A structure for delivering power is described. In some embodiments, the structure can include conductors disposed on two or more layers. Specifically, the structure can include a first set of interdigitated conductors disposed on a first layer and oriented substantially along an expected direction of current flow. At least one conductor in the first set of interdigitated conductors may be maintained at a first voltage, and at least one conductor in the first set of interdigitated conductors may be maintained at a second voltage, wherein the second voltage is different from the first voltage. The structure may further include a conducting structure disposed on a second layer, wherein the second layer is different from the first layer, and wherein at least one conductor in the conducting structure is maintained at the first voltage.Type: ApplicationFiled: December 11, 2023Publication date: June 27, 2024Applicant: Rambus Inc.Inventors: Kyung Suk Oh, Ralf M. Schmitt, Yijong Feng
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Patent number: 12020740Abstract: An integrated circuit memory device includes an array of storage cells configured into multiple banks. Each bank includes multiple segments. Register storage stores per-segment values representing per-segment refresh parameters. Refresh logic refreshes each segment in accordance with the corresponding per-segment value.Type: GrantFiled: May 25, 2019Date of Patent: June 25, 2024Assignee: Rambus Inc.Inventor: Thomas Vogelsang
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Patent number: 12014089Abstract: Memory devices and a memory controller that controls such memory devices. Multiple memory devices receive commands and addresses on a command/address (C/A) bus that is relayed point-to-point by each memory device. Data is received and sent from these devices to/from a memory controller in a point-to-point configuration by adjusting the width of each individual data bus coupled between the individual memory devices and the memory controller. Along with the C/A bus are clock signals that are regenerated by each memory device and relayed. The memory controller and memory devices may be packaged on a single substrate using package-on-package technology. Using package-on-package technology allows the relayed C/A signals to connect from memory device to memory device using wire bonding. Wirebond connections provide a short, high-performance signaling environment for the chip-to-chip relaying of the C/A signals and clocks from one memory device to the next in the daisy-chain.Type: GrantFiled: March 14, 2023Date of Patent: June 18, 2024Assignee: Rambus Inc.Inventor: Frederick Ware
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Patent number: 12007916Abstract: A memory controller interfaces with one or more memory devices having configurable width data buses and configurable connectivity between data pins of the memory devices and data pins of the memory controller. Upon initialization of the memory devices, the memory controller automatically discovers the connectivity configuration of the one or more memory devices, including both individually selected and jointly selected devices. After discovering connectivity of the connected devices, the memory controller configures the memory devices according to the discovered connectivity and assigns unique addresses to jointly selected devices.Type: GrantFiled: April 3, 2023Date of Patent: June 11, 2024Assignee: RAMBUS INC.Inventor: John Eric Linstadt
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Patent number: 12001697Abstract: A memory system includes two or more memory controllers capable of accessing the same dynamic, random-access memory (DRAM), one controller having access to the DRAM or a subset of the DRAM at a time. Different subsets of the DRAM are supported with different refresh-control circuitry, including respective refresh-address counters. Whichever controller has access to a given subset of the DRAM issues refresh requests to the corresponding refresh-address counter. Counters are synchronized before control of a given subset of the DRAM is transferred between controllers to avoid a loss of stored data.Type: GrantFiled: October 15, 2021Date of Patent: June 4, 2024Assignee: Rambus Inc.Inventors: Thomas Vogelsang, Steven C. Woo, Michael Raymond Miller
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Patent number: 12001283Abstract: Data and error correction information may involve accessing multiple data channels (e.g., 8) and one error detection and correction channel concurrently. This technique requires a total of N+1 row requests for each access, where N is the number of data channels (e.g., 8 data row accesses and 1 error detection and correction row access equals 9 row accesses.) A single (or at least less than N) data channel row may be accessed concurrently with a single error detection and correction row. This reduces the number of row requests to two (2)—one for the data and one for the error detection and correction information. Because, row requests consume power, reducing the number of row requests is more power efficient.Type: GrantFiled: April 4, 2023Date of Patent: June 4, 2024Assignee: Rambus Inc.Inventors: Michael Raymond Miller, Stephen Magee, John Eric Linstadt
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Patent number: 12002540Abstract: A memory device includes a set of inputs, and a first register that includes a first register field to store a value for enabling application of one of a plurality of command/address (CA) on-die termination (ODT) impedance values to first inputs that receive the CA signals; and a second register field to store a value for enabling application of one of a plurality of chip select (CS) ODT impedance values to a second input that receives the CS signal. A third register field may store a value for enabling application of a clock (CK) ODT impedance value to third inputs that receive the CK signal.Type: GrantFiled: June 26, 2023Date of Patent: June 4, 2024Assignee: RAMBUS INC.Inventors: Ian Shaeffer, Kyung Suk Oh
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Patent number: 12002506Abstract: A DRAM device may be configured to retransmit or not retransmit zero or more of command/address signals, write data signals, read data signals, and/or data strobe signals. The DRAM device may have separate, unidirectional read data signal and write data signal interfaces. Combined activate and read or write commands may be implemented. The configuration of the DRAM to retransmit or not retransmit signals may be determined by the DRAM device's physical location on a module via hardwired configuration pins. The various configurations allows a DRAM device to be used on both a long and narrow form factor module and a DIMM module.Type: GrantFiled: April 25, 2022Date of Patent: June 4, 2024Assignee: Rambus Inc.Inventor: Torsten Partsch
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Patent number: 12002532Abstract: A memory component and a controller communicate commands and data with each other The commands to activate and then access data, and the data itself, are all communicated between a controller and the memory component at different times. The controller and memory component each calculate a respective error detecting code (EDC) values on the activate command information (e.g., bank address and row address) and store them indexed by the bank address. When the memory component is accessed, retrieved EDC values are combined with EDC values calculated from the access command information, and the data itself. The memory component transmits its combined EDC value to the controller for checking.Type: GrantFiled: March 14, 2023Date of Patent: June 4, 2024Assignee: Rambus Inc.Inventors: John Eric Linstadt, Frederick A. Ware
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Patent number: 12002513Abstract: Control logic within a memory control component outputs first and second memory read commands to a memory module at respective times, the memory module having memory components disposed thereon. Interface circuitry within the memory control component receives first read data concurrently from a first plurality of the memory components via a first plurality of data paths, respectively, in response to the first memory read command, and receives second read data concurrently from a second plurality of the memory components via a second plurality of data paths, respectively, in response to the second memory read command, the first plurality of the memory components including at least one memory component not included in the second plurality of the memory components and vice-versa.Type: GrantFiled: January 3, 2022Date of Patent: June 4, 2024Assignee: Rambus Inc.Inventors: Gary B. Bronner, Brent Steven Haukness, Mark A. Horowitz, Mark D. Kellam, Fariborz Assaderaghi
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Patent number: 11994930Abstract: Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.Type: GrantFiled: May 19, 2022Date of Patent: May 28, 2024Assignee: Rambus Inc.Inventors: Dinesh Patil, Amir Amirkhany, Farrukh Aquil, Kambiz Kaviani, Frederick A. Ware