Patents Assigned to Rambus
-
Patent number: 10873321Abstract: Disclosed is receiver for a noise limited system. A front-end circuit amplifies and band-limits an incoming signal. The amplification increases the signal swing but introduces both thermal and flicker noise. A low-pass band limitation reduces the thermal noise component present at frequencies above what is necessary for correctly receiving the transmitted symbols. This band limited signal is provided to the integrator circuit. The output of the integrator is equalized to reduce the effects of inter-symbol interference and then sampled. The samples are used to apply low frequency equalization (i.e., in response to long and/or unbalanced strings of symbols) to mitigate the effects of DC wander caused by mismatches between the number of symbols of each kind being received.Type: GrantFiled: June 15, 2020Date of Patent: December 22, 2020Assignee: Rambus Inc.Inventors: Masum Hossain, Carl W. Werner
-
Patent number: 10867691Abstract: A controller includes an internal memory to store an address and a memory control unit operatively coupled with the internal memory. The memory control unit includes logic to identify a malfunctioning address of primary data storage elements within an external memory device, the external memory device being another semiconductor device separate from the controller, store the malfunctioning address in the internal memory, and transmit, to the external memory device, a command to initiate a repair of the malfunctioning address using redundant data storage elements and an indication of an address associated with the malfunctioning address.Type: GrantFiled: October 11, 2019Date of Patent: December 15, 2020Assignee: Rambus Inc.Inventors: Adrian E. Ong, Fan Ho
-
Patent number: 10866916Abstract: A memory module comprises a data interface including a plurality of data lines and a plurality of configurable switches coupled between the data interface and a data path to one or more memories. The effective width of the memory module can be configured by enabling or disabling different subsets of the configurable switches. The configurable switches may be controlled by manual switches, by a buffer on the memory module, by an external memory controller, or by the memories on the memory module.Type: GrantFiled: July 29, 2019Date of Patent: December 15, 2020Assignee: Rambus Inc.Inventors: Amir Amirkhany, Suresh Rajan, Ravindranath Kollipara, Ian Shaeffer, David A. Secker
-
Patent number: 10861554Abstract: A memory system includes an array of non-volatile memory cells and a memory controller having a first port to receive a program command that addresses a number of the memory cells for a programming operation, having a second port coupled to the memory array via a command pipeline, and configured to create a plurality of fractional program commands in response to the program command. Execution of each fractional program command applies a single program pulse to the addressed memory cells to incrementally program the addressed memory cells with program data, where the duration of the program pulse associated with each fractional program command is a selected fraction of the total programming time typically required to program the memory cells.Type: GrantFiled: April 18, 2018Date of Patent: December 8, 2020Assignee: Rambus Inc.Inventors: Brent S. Haukness, Ian Shaeffer, Gary Bela Bronner
-
Patent number: 10860253Abstract: An memory component includes a memory bank and a command interface to receive a read-modify-write command, having an associated read address indicating a location in the memory bank and to either access read data from the location in the memory bank indicated by the read address after an adjustable delay period transpires from a time at which the read-modify-write command was received or to overlap multiple read-modify-write commands. The memory component further includes a data interface to receive write data associated with the read-modify-write command and an error correction circuit to merge the received write data with the read data to form a merged data and write the merged data to the location in the memory bank indicated by the read address.Type: GrantFiled: April 1, 2019Date of Patent: December 8, 2020Assignee: Rambus Inc.Inventors: Frederick A. Ware, Thomas Vogelsang
-
Patent number: 10860216Abstract: A memory is disclosed comprising a first memory portion, a second memory portion, and an interface, wherein the memory portions are electrically isolated from each other and the interface is capable of receiving a row command and a column command in the time it takes to cycle the memory once. By interleaving access requests (comprising row commands and column commands) to the different portions of the memory, and by properly timing these access requests, it is possible to achieve full data bus utilization in the memory without increasing data granularity.Type: GrantFiled: October 31, 2018Date of Patent: December 8, 2020Assignee: Rambus Inc.Inventor: Billy Garrett, Jr.
-
Patent number: 10861532Abstract: An integrated circuit (IC) memory controller is disclosed. The memory controller includes a receiver to receive a strobe signal and provide an internal strobe signal. An adjustable delay circuit delays an enable signal to generate a delayed enable signal. A gate circuit generates a gated strobe signal using the delayed enable signal that masks transitions of the internal strobe signal that occur prior to a valid region of the internal strobe signal. A sample circuit samples data using the gated strobe signal.Type: GrantFiled: December 23, 2019Date of Patent: December 8, 2020Assignee: Rambus Inc.Inventors: Jade M. Kizer, Sivakumar Doraiswamy, Benedict Lau
-
Patent number: 10854652Abstract: An array of diffraction-pattern generators employ phase anti-symmetric gratings to projects near-field spatial modulations onto a closely spaced array of photoelements. Each generator in the array of generators produces point-spread functions with spatial frequencies and orientations of interest. The generators are arranged in an irregular mosaic with little or no short-range repetition. Diverse generators are shaped and placed with some irregularity to reduce or eliminate spatially periodic replication of ambiguities to facilitate imaging of nearby scenes.Type: GrantFiled: January 3, 2018Date of Patent: December 1, 2020Assignee: Rambus Inc.Inventors: Patrick R. Gill, David G. Stork
-
Patent number: 10855297Abstract: A phase rotator receives control signals and thermometer coded signals that specifies the phase of an output signal. The phase rotator may be used, for example, by a clock and data recovery (CDR) circuit to continually rotate the phase of a clock to compensate for phase/frequency mismatches between received data and the clock. The control signals determine the phase quadrant (i.e., 0°-90°, 90°-180°, etc.) of the output signal. The thermometer coded signals determine the phase of the output signal within a quadrant by steering a set of bias currents between two or more nodes. The set of bias currents are selected to reduce the non-linearity between the thermometer coded value and the phase of the output signal.Type: GrantFiled: June 14, 2019Date of Patent: December 1, 2020Assignee: Rambus Inc.Inventors: Marcus Van Ierssel, Dominic Diclemente
-
Patent number: 10855496Abstract: An integrated circuit (IC) memory device includes receiver circuitry to receive write data from a memory controller. The receiver circuitry includes equalization circuitry having at least one tap to equalize the write data. The equalization circuitry includes a tap weight adapter circuit to adaptively generate a tap weight for the tap from an edge analysis of previously received write data.Type: GrantFiled: August 7, 2018Date of Patent: December 1, 2020Assignee: Rambus Inc.Inventors: Brian S. Leibowitz, Hae-Chang Lee, Jihong Ren, Ruwan Ratnayake
-
Patent number: 10853265Abstract: A memory system includes an address mapping circuit. The address mapping circuit receives an input memory address having a first set of address bits. The address mapping circuit applies a logic function to the input memory address to generate a mapped memory address. The logic function uses at least a subset of the first set of address bits in two separate operations that respectively determine two portions of the mapped memory address.Type: GrantFiled: September 18, 2018Date of Patent: December 1, 2020Assignee: Rambus Inc.Inventors: Hongzhong Zheng, James Tringali
-
Patent number: 10855413Abstract: A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a reference. The receive circuit compares the patterns. Any differences between the patterns are observable. In one embodiment, a linear feedback shift register (LFSR) is implemented to produce patterns. An embodiment of the present disclosure may be practiced with various types of signaling systems, including those with single-ended signals and those with differential signals. An embodiment of the present disclosure may be applied to systems communicating a single bit of information on a single conductor at a given time and to systems communicating multiple bits of information on a single conductor simultaneously.Type: GrantFiled: April 29, 2016Date of Patent: December 1, 2020Assignee: Rambus Inc.Inventors: Jared Zerbe, Pak Shing Chau, William Franklin Stonecypher
-
Patent number: 10846835Abstract: An optical method of measuring motion employs a phase grating that produces a diffraction pattern responsive to light from an imaged scene. First and second images of the diffraction pattern are captured and compared to produce an image comparison. Apparent motion is then calculated from the image comparison.Type: GrantFiled: December 21, 2018Date of Patent: November 24, 2020Assignee: Rambus Inc.Inventors: Patrick R. Gill, David G. Stork, Patrick R. Johnstone
-
Patent number: 10848350Abstract: This disclosure provides a split-path equalizer and a clock recovery circuit. More particularly, clock recovery operation is enhanced, particularly at high-signaling rates, by separately equalizing each of a data path and an edge path. In specific embodiments, the data path is equalized in a manner that maximizes signal-to-noise ratio and the edge path is equalized in a manner that emphasizes symmetric edge response for a single unit interval and zero edge response for other unit intervals (e.g., irrespective of peak voltage margin). Such equalization tightens edge grouping and thus enhances clock recovery, while at the same time optimizing data-path sampling. Techniques are also disclosed for addressing split-path equalization-induced skew.Type: GrantFiled: June 17, 2016Date of Patent: November 24, 2020Assignee: Rambus Inc.Inventors: Masum Hossain, Jared L. Zerbe
-
Patent number: 10847196Abstract: A memory module includes cache of relatively fast and durable dynamic, random-access memory (DRAM) in service of a larger amount of relatively slow and wear-sensitive nonvolatile memory. Local controller manages communication between the DRAM cache and nonvolatile memory to accommodate disparate access granularities, reduce the requisite number of memory transactions, and minimize the flow of data external to nonvolatile memory components.Type: GrantFiled: October 10, 2017Date of Patent: November 24, 2020Assignee: Rambus Inc.Inventors: Frederick A. Ware, John Eric Linstadt, Kenneth L. Wright
-
Patent number: 10846006Abstract: Same sized blocks of data corresponding to a single read/write command are stored in the same memory array of a memory device, but using different formats. A first one of these formats spreads the data in the block across a larger number of memory subarrays (a.k.a., memory array tiles—MATs) than a second format. In this manner, the data blocks stored in the first format can be accessed with lower latency than the blocks stored in the second format because more data can be read from the array simultaneously. In addition, since the data stored in the second format is stored in fewer subarrays, it takes less energy to read a block stored in the second format. Thus, a system may elect, on a data block by data block basis, whether to conserve power or improve speed.Type: GrantFiled: July 22, 2019Date of Patent: November 24, 2020Assignee: Rambus Inc.Inventors: Frederick A. Ware, John Eric Linstadt
-
Patent number: 10840920Abstract: A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.Type: GrantFiled: December 2, 2019Date of Patent: November 17, 2020Assignee: Rambus Inc.Inventors: Jared L. Zerbe, Brian S. Leibowitz, Hsuan-Jung Su, John Cronan Eble, III, Barry William Daly, Lei Luo, Teva J. Stone, John Wilson, Jihong Ren, Wayne D. Dettloff
-
Patent number: 10840974Abstract: An integrated-circuit output driver generates, in response to an input signal constrained to a first voltage range, a control signal at one of two voltage levels according to a data bit conveyed in the input signal, the two voltages levels defining upper and lower levels of a second voltage range substantially larger than the first voltage range. The output driver generates an output-drive signal constrained to a third voltage range according to the one of the two voltage levels of the control signal, the third voltage range being substantially smaller than the second voltage range.Type: GrantFiled: April 1, 2019Date of Patent: November 17, 2020Assignee: Rambus Inc.Inventors: Frederick A. Ware, Carl W. Werner
-
Patent number: 10839863Abstract: In a data transmission system, one or more signal supply voltages for generating the signaling voltage of a signal to be transmitted are generated in a first circuit and forwarded from the first circuit to a second circuit. The second circuit may use the forwarded signal supply voltages to generate another signal to be transmitted back from the second circuit to the first circuit, thereby obviating the need to generate signal supply voltages separately in the second circuit. The first circuit may also adjust the signal supply voltages based on the signal transmitted back from the second circuit to the first circuit. The data transmission system may employ a single-ended signaling system in which the signaling voltage is referenced to a reference voltage that is a power supply voltage such as ground, shared by the first circuit and the second circuit.Type: GrantFiled: November 26, 2019Date of Patent: November 17, 2020Assignee: Rambus Inc.Inventors: Scott C. Best, John W. Poulton
-
Patent number: 10841138Abstract: A hybrid voltage mode (VM) and current mode (CM) four-level pulse amplitude modulation (PAM-4) transmitter circuits (a.k.a. drivers) is calibrated using a configurable replica circuit and calibration control circuitry. The replica circuit includes an on-chip termination impedance to mimic a receiver's termination impedance. The amount of level enhancement provided by the current mode circuitry is calibrated by adjusting the current provided to the output node and sunk from the output node by the replica current mode circuitry while the replica voltage mode circuitry is driving an intermediate PAM-4 level. After the level enhancement has been set, the non-linearity between levels is calibrated by adjusting the amount of current provided to the output node by the replica current mode circuitry while the replica voltage mode circuitry is driving a maximum output voltage level.Type: GrantFiled: June 14, 2019Date of Patent: November 17, 2020Assignee: Rambus Inc.Inventors: Kamran Farzan, Aaron Ali