Patents Assigned to Rambus
  • Structure for delivering power
    Patent number: 10674597
    Abstract: A structure for delivering power is described. In some embodiments, the structure can include conductors disposed on two or more layers. Specifically, the structure can include a first set of interdigitated conductors disposed on a first layer and oriented substantially along an expected direction of current flow. At least one conductor in the first set of interdigitated conductors may be maintained at a first voltage, and at least one conductor in the first set of interdigitated conductors may be maintained at a second voltage, wherein the second voltage is different from the first voltage. The structure may further include a conducting structure disposed on a second layer, wherein the second layer is different from the first layer, and wherein at least one conductor in the conducting structure is maintained at the first voltage.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: June 2, 2020
    Assignee: Rambus Inc.
    Inventors: Kyung Suk Oh, Ralf M. Schmitt, Yijiong Feng
  • Image sensor having sub-diffraction-limit pixels
    Patent number: 10674098
    Abstract: An imaging system has an imager comprising a plurality of jots. A readout circuit is in electrical communication with the imager. The readout circuit can be configured to facilitate the formation of an image by defining neighborhoods of the jots, wherein a local density of exposed jots within a neighborhood is used to generate a digital value for a pixel of the image.
    Type: Grant
    Filed: December 26, 2016
    Date of Patent: June 2, 2020
    Assignee: Rambus Inc.
    Inventor: Eric R. Fossum
  • Protocol for memory power-mode control
    Patent number: 10672450
    Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: June 2, 2020
    Assignee: Rambus Inc.
    Inventors: Wayne F. Ellis, Wayne S. Richardson, Akash Bansal, Frederick A. Ware, Lawrence Lai, Kishore Ven Kasamsetty
  • Communication channel calibration for drift conditions
    Patent number: 10673582
    Abstract: A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: June 2, 2020
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Richard E. Perego, Craig E. Hampel
  • Memory repair method and apparatus based on error code tracking
    Patent number: 10664344
    Abstract: A memory module is disclosed that includes a substrate, a memory device that outputs read data, and a buffer. The buffer has a primary interface for transferring the read data to a memory controller and a secondary interface coupled to the memory device to receive the read data. The buffer includes error logic to identify an error in the received read data and to identify a storage cell location in the memory device associated with the error. Repair logic maps a replacement storage element as a substitute storage element for the storage cell location associated with the error.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: May 26, 2020
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Ely Tsern
  • Memory component with independently enabled data and command interfaces
    Patent number: 10665289
    Abstract: An integrated circuit includes a physical layer interface having a control timing domain and a data timing domain, and circuits that enable the control timing domain during a change in power conservation mode in response to a first event, and that enable the data timing domain in response to a second event. The control timing domain can include interface circuits coupled to a command and address path, and the data timing domain can include interface circuits coupled to a data path.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: May 26, 2020
    Assignee: Rambus Inc.
    Inventors: Ian Shaeffer, Lei Luo, Liji Gopalakrishnan
  • Calibration methods and circuits to calibrate drive current and termination impedance
    Patent number: 10666254
    Abstract: Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termination resistances and drive currents to produce optimal output swing voltages. Comparison circuitry employed to calibrate the reference resistance is also used to calibrate the drive current. Termination elements in some embodiments are divided into two adjustable resistive portions, both of which are designed to minimize capacitive loading. One portion is optimized to produce a relatively high range of adjustment, while the other is optimized for fine-tuning and glitch-free switching.
    Type: Grant
    Filed: March 18, 2019
    Date of Patent: May 26, 2020
    Assignee: Rambus Inc.
    Inventors: Huy M. Nguyen, Vijay Gadde, Benedict Lau
  • Reduced current memory device
    Patent number: 10658037
    Abstract: A memory device may include a local bit line electrically coupled to a plurality of memory cells and a global bit line electrically coupled to the local bit line through first and second selectable parallel paths having first and second impedances, respectively. The first path may be active and the second path may be in an off state in at least one of a set operation or a forming operation. The second path may be active in a reset operation, wherein the second impedance of the second path has a lower impedance than the first impedance of the first path.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: May 19, 2020
    Assignee: Rambus Inc.
    Inventors: Deepak Chandra Sekar, Brent S. Haukness, Bruce L. Bateman
  • Integrated circuit comprising circuitry to change a clock signal frequency while a data signal is valid
    Patent number: 10659024
    Abstract: Methods and apparatuses for communicating information are described. In some embodiments, a first integrated circuit (IC) provides a clock signal and a data signal to a second IC, wherein the data bits of the data signal are timed according to the clock signal, and wherein the frequency of the clock signal is capable of being changed even when the data signal is valid.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: May 19, 2020
    Assignee: Rambus Inc.
    Inventors: Brian Hing-Kit Tsang, Jared L. Zerbe
  • Fractional-readout oversampled image sensor
    Patent number: 10659715
    Abstract: Signals representative of total photocharge integrated within respective image-sensor pixels are read out of the pixels after a first exposure interval that constitutes a first fraction of a frame interval. Signals in excess of a threshold level are read out of the pixels after an ensuing second exposure interval that constitutes a second fraction of the frame interval, leaving residual photocharge within the pixels. After a third exposure interval that constitutes a third fraction of the frame interval, signals representative of a combination of at least the residual photocharge and photocharge integrated within the pixels during the third exposure interval are read out of the pixels.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: May 19, 2020
    Assignee: Rambus Inc.
    Inventors: Jay Endsley, Thomas Vogelsang, Craig M. Smith, Michael Guidash, Alexander C. Schneider
  • Systems and methods for lensed and lensless optical sensing of binary scenes
    Patent number: 10653313
    Abstract: A sensing device with an odd-symmetry grating projects near-field spatial modulations onto an array of closely spaced pixels. Due to physical properties of the grating, the spatial modulations are in focus for a range of wavelengths and spacings. The spatial modulations are captured by the array, and photographs and other image information can be extracted from the resultant data. Pixels responsive to infrared light can be used to make thermal imaging devices and other types of thermal sensors. Some sensors are well adapted for tracking eye movements, and others for imaging barcodes and like binary images. In the latter case, the known binary property of the expected images can be used to simplify the process of extracting image data.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: May 19, 2020
    Assignee: Rambus Inc.
    Inventors: Patrick R. Gill, David G. Stork
  • Amplifier circuit for cryogenic applications
    Patent number: 10658987
    Abstract: The embodiments herein describe technologies of an amplifier circuit that is designed for wideband communication with superconductive components in cryogenic applications, including Josephson Junction integrated circuits, operating in a cryogenic temperature domain (e.g., 4K). The amplifier circuit operates in a temperature domain (e.g., 77K) that is higher than the cryogenic temperature domain of the superconductive components.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: May 19, 2020
    Assignee: Rambus Inc.
    Inventors: Richelle L. Smith, Roxanne Vu, Carl W. Werner
  • Selectable-tap equalizer
    Patent number: 10652052
    Abstract: A signaling circuit having a selectable-tap equalizer. The signaling circuit includes a buffer, a select circuit and an equalizing circuit. The buffer is used to store a plurality of data values that correspond to data signals transmitted on a signaling path during a first time interval. The select circuit is coupled to the buffer to select a subset of data values from the plurality of data values according to a select value. The equalizing circuit is coupled to receive the subset of data values from the select circuit and is adapted to adjust, according to the subset of data values, a signal level that corresponds to a data signal transmitted on the signaling path during a second time interval.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: May 12, 2020
    Assignee: Rambus Inc.
    Inventors: Jared L. Zerbe, Vladimir M. Stojanovic, Fred F. Chen
  • Multi-bit symbol reception using remotely-sourced reference signals
    Patent number: 10649478
    Abstract: An integrated circuit component receives an input signal via an external signal conduction path during a first interval and transmits an output signal via the external signal conduction path during a second interval. The integrated circuit component terminates the input signal and the output signal within one or more termination elements having an impedance in accordance with a characteristic impedance of the external signal conduction path to obviate signal termination within another integrated circuit component to which the output signal is destined and from which the input signal is sourced.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: May 12, 2020
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, John Eric Linstadt
  • Methods and systems for reducing image artifacts
    Patent number: 10652435
    Abstract: An imaging system with a diffractive optic captures an interference pattern responsive to light from an imaged scene to represent the scene in a spatial-frequency domain. The sampled frequency-domain image data has properties that are determined by the point-spread function of diffractive optic and characteristics of scene. An integrated processor can modified the sampled frequency-domain image data responsive to such properties before transforming the modified frequently-domain image data into the pixel domain.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: May 12, 2020
    Assignee: Rambus Inc.
    Inventors: Patrick R. Gill, Thomas Vogelsang
  • Low-noise, high dynamic-range image sensor
    Patent number: 10652493
    Abstract: A sequence of control voltage levels are applied to a control signal line capacitively coupled to a floating diffusion node of a pixel to sequentially adjust a voltage level of the floating diffusion node. A pixel output signal representative of the voltage level of the floating diffusion node is compared with a reference voltage to identify a first control voltage level of the sequence of control voltage levels for which the voltage level of the floating diffusion node exceeds the reference voltage.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: May 12, 2020
    Assignee: Rambus Inc.
    Inventors: John Ladd, Michael Guidash, Craig M. Smith, Thomas Vogelsang, Jay Endsley, Michael T. Ching, James E. Harris
  • Variable width memory module supporting enhanced error detection and correction
    Patent number: 10650881
    Abstract: Described are memory modules that support different error detection and correction (EDC) schemes in both single- and multiple-module memory systems. The memory modules are width configurable and support the different EDC schemes for relatively wide and narrow module data widths. Data buffers on the modules support the half-width and full-width modes, and also support time-division-multiplexing to access additional memory components on each module in support of enhanced EDC.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: May 12, 2020
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, John Eric Linstadt, Kenneth L. Wright
  • Integrated circuit with configurable on-die termination
    Patent number: 10651848
    Abstract: Described are integrated-circuit die with differential receivers, the inputs of which are coupled to external signal pads. Termination legs coupled to the signal pads support multiple termination topologies. These termination legs can support adjustable impedances, capacitances, or both, which may be controlled using an integrated memory.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: May 12, 2020
    Assignee: Rambus Inc.
    Inventor: Huy Nguyen
  • Transaction-based on-die termination
    Patent number: 10651849
    Abstract: A memory control component outputs a memory write command to a memory IC and also outputs write data to be received via data inputs of the memory IC. Prior to reception of the write data within the memory IC, the memory control component asserts a termination control signal that causes the memory IC to apply to the data inputs a first on-die termination impedance during reception of the write data followed by a second on-die termination impedance after the write data has been received. The memory control component deasserts the termination control signal to cause the memory IC to apply no termination impedance to the data inputs.
    Type: Grant
    Filed: March 18, 2019
    Date of Patent: May 12, 2020
    Assignee: Rambus Inc.
    Inventors: Kyung Suk Oh, Ian P. Shaeffer
  • Memory component with multiple command/address sampling modes
    Patent number: 10650872
    Abstract: In a multirank memory system in which the clock distribution trees of each rank are permitted to drift over a wide range (e.g., low power memory systems), the fine-interleaving of commands between ranks is facilitated through the use of techniques that cause each addressed rank to properly sample commands intended for that rank, notwithstanding the drift. The ability to perform such “microthreading” provides for substantially enhanced memory capacity without sacrificing the performance of single rank systems. This disclosure provides methods, memory controllers, memory devices and system designs adapted to these ends.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: May 12, 2020
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Ely K. Tsern, Brian S. Leibowitz, Wayne Frederick Ellis, Akash Bansal, John Welsford Brooks, Kishore Ven Kasamsetty