Patents Assigned to Rambus
  • Verify before program resume for memory devices
    Patent number: 10445226
    Abstract: A method of programming data into a memory device including an array of memory cells is disclosed. The method comprises receiving at least one program command that addresses a number of the memory cells for a programming operation to program data in the memory cells. The at least one program command is executed by iteratively carrying out at least one program/verify cycle to incrementally program the addressed memory cells with the program data. A secondary command may be selectively received after initiating but before completing the programming operation. The programming operation may be selectively resumed by first verifying the memory cells, then carrying out at least one program/verify cycle.
    Type: Grant
    Filed: August 4, 2011
    Date of Patent: October 15, 2019
    Assignee: Rambus Inc.
    Inventors: Ian Shaeffer, Brent S. Haukness
  • Signaling system with adaptive timing calibration
    Patent number: 10447465
    Abstract: A signaling system is disclosed. The signaling system includes a first integrated circuit (IC) chip to receive a data signal and a strobe signal. The first IC includes circuitry to sample the data signal at times indicated by the strobe signal to generate phase error information and circuitry to output the phase error information from the first IC device. The system further includes a signaling link and a second IC chip coupled to the first IC chip via the signaling link to output the data signal and the strobe signal to the first IC chip. The second IC chip includes delay circuitry to generate the strobe signal by delaying an aperiodic timing signal for a first time interval and timing control circuitry to receive the phase error information from the first IC chip and adjust the first time interval in accordance with the phase error information.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: October 15, 2019
    Assignee: Rambus Inc.
    Inventors: Bret G. Stott, Craig E. Hampel, Frederick A. Ware
  • Controller to detect malfunctioning address of memory device
    Patent number: 10446256
    Abstract: A controller includes an internal memory to store an address and a memory control unit operatively coupled with the internal memory. The memory control unit includes logic to identify a malfunctioning address of primary data storage elements within an external memory device, the external memory device being another semiconductor device separate from the controller, store the malfunctioning address in the internal memory, and transmit, to the external memory device, a command to initiate a repair of the malfunctioning address using redundant data storage elements and an indication of an address associated with the malfunctioning address.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: October 15, 2019
    Assignee: Rambus Inc.
    Inventors: Adrian E. Ong, Fan Ho
  • Memory mirroring
    Patent number: 10437685
    Abstract: Described is memory system enabling memory mirroring in single write operations for the primary and backup data storage. The memory system utilizes a memory channel including one or more latency groups, with each latency group encompassing a number of memory modules that have the same signal timing to the controller. A primary copy and a backup copy of a data element can be written to two memory modules in the same latency group of the channel and in a single write operation. The buses of the channel may have the same trace length to each of the memory modules within a latency group.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: October 8, 2019
    Assignee: Rambus Inc.
    Inventors: Steven Woo, David A. Secker, Ravindranath Kollipara
  • Communication channel calibration using feedback
    Patent number: 10439740
    Abstract: A method for calibrating a communication channel coupling first and second components includes transmitting a data signal from the first component to the second component on the communication channel, and sensing a characteristic, such as phase, of the data signal on the second component. Information about the sensed characteristic is fed back to the first component using an auxiliary channel. An adjustable parameter, such as phase, for the transmitter is adjusted on the first component in response to the information. Also, a characteristic of a data signal received from the transmitter on the second component is sensed and used to adjust an adjustable parameter for the receiver on the first component.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: October 8, 2019
    Assignee: Rambus Inc.
    Inventors: Jun Kim, Wayne S. Richardson, Glenn Chiu
  • Memory appliance couplings and operations
    Patent number: 10437747
    Abstract: System and method for improved transferring of data involving memory device systems. A memory appliance (MA) comprising a plurality of memory modules is configured to store data within the plurality of memory modules and further configured to receive data commands from first server and a second server coupled to the MA. The data commands may include direction memory access commands such that the MA can service the data commands while bypassing a host controller of the MA.
    Type: Grant
    Filed: April 11, 2016
    Date of Patent: October 8, 2019
    Assignee: Rambus Inc.
    Inventors: Vlad Fruchter, Keith Lowery, George Michael Uhler, Steven Woo, Chi-Ming (Philip) Yeung, Ronald Lee
  • Protocol for memory power-mode control
    Patent number: 10431290
    Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: October 1, 2019
    Assignee: Rambus Inc.
    Inventors: Wayne F. Ellis, Wayne S. Richardson, Akash Bansal, Frederick A. Ware, Lawrence Lai, Kishore Ven Kasamsetty
  • Memory controller systems with nonvolatile memory for storing operating parameters
    Patent number: 10430092
    Abstract: The present invention is directed to computer storage systems and methods thereof. In an embodiment, a memory system comprises a controller module, a nonvolatile memory, and a volatile memory. The controller module operates according to a command and operation table. The command and operation table can be updated to change the way controller module operates. When the command and operation table is updated, the updated table is stored at a predefined location of the nonvolatile memory. There are other embodiments as well.
    Type: Grant
    Filed: July 28, 2014
    Date of Patent: October 1, 2019
    Assignee: Rambus Inc.
    Inventors: Shih-ho Wu, Christopher Haywood
  • Receiver with enhanced clock and data recovery
    Patent number: 10432389
    Abstract: A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: October 1, 2019
    Assignee: Rambus Inc.
    Inventors: Hae-Chang Lee, Brian Leibowitz, Jaeha Kim, Jafar Savoj
  • Low-power source-synchronous signaling
    Patent number: 10418089
    Abstract: A method of operating a memory controller is disclosed. The method includes transmitting data signals to a memory device over each one of at least two parallel data links. A timing signal is sent to the memory device on a first dedicated link. The timing signal has a fixed phase relationship with the data signals. A data strobe signal is driven to the memory device on a second dedicated link. Phase information is received from the memory device. The phase information being generated internal to the memory device and based on a comparison between the timing signal and a version of the data strobe signal internally distributed within the memory device. A phase of the data strobe signal is adjusted relative to the timing signal based on the received phase information.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: September 17, 2019
    Assignee: Rambus Inc.
    Inventors: Jared L. Zerbe, Frederick A. Ware
  • High speed signaling system with adaptive transmit pre-emphasis
    Patent number: 10411923
    Abstract: A high-speed signaling system with adaptive transmit pre-emphasis. A transmit circuit has a plurality of output drivers to output a first signal onto a signal path. A receive circuit is coupled to receive the first signal via the signal path and configured to generate an indication of whether the first signal exceeds a threshold level. A first threshold control circuit is coupled to receive the indication from the receive circuit and configured to adjust the threshold level according to whether the first signal exceeds the threshold level. A drive strength control circuit is coupled to receive the indication from the receive circuit and configured to adjust a drive strength of at least one output driver of the plurality of output drivers according to whether the first signal exceeds the threshold level.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: September 10, 2019
    Assignee: Rambus Inc.
    Inventors: Vladimir M. Stojanovic, Andrew C. Ho, Anthony Bessios, Fred F. Chen, Elad Alon, Mark A. Horowitz
  • Interface for memory readout from a memory component in the event of fault
    Patent number: 10409742
    Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, an integrated circuit (IC) memory component is disclosed that includes a memory core, a primary interface, and a secondary interface. The primary interface includes data input/output (I/O) circuitry and control/address (C/A) input circuitry, and accesses the memory core during a normal mode of operation. The secondary interface accesses the memory core during a fault mode of operation.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: September 10, 2019
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Kenneth L. Wright
  • Integrated circuit device having an injection-locked oscillator
    Patent number: 10404258
    Abstract: A variable injection-strength injection-locked oscillator (ILO) is described. The variable injection-strength ILO can output an output clock signal based on an input clock signal. The variable injection-strength ILO can pause, restart, slow down, or speed up the output clock signal synchronously with respect to the input clock signal in response to receiving power mode information. Specifically, the variable injection-strength ILO can be operated under relatively strong injection when the input clock signal is paused, restarted, slowed down, or sped up.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: September 3, 2019
    Assignee: Rambus Inc.
    Inventors: Marko Aleksić, Brian S. Leibowitz
  • Integrated circuit having a multiplying injection-locked oscillator
    Patent number: 10404262
    Abstract: Methods and apparatuses featuring a multiplying injection-locked oscillator are described. Some embodiments include a pulse-generator-and-injector and one or more injection-locked oscillators. The outputs of the pulse-generator-and-injector can be injected into corresponding injection points of an injection-locked oscillator. In embodiments that include multiple injection-locked oscillators, the outputs of each injection-locked oscillator can be injected into the corresponding injection points of the next injection-locked oscillator. Some embodiments reduce deterministic jitter by dynamically modifying the loop length of an injection-locked oscillator, and/or by using a duty cycle corrector, and/or by multiplexing/blending the outputs from multiple delay elements of an injection-locked oscillator.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: September 3, 2019
    Assignee: Rambus Inc.
    Inventors: Jared L. Zerbe, Barry W. Daly, Dustin T. Dunwell, Anthony C. Carusone, John C. Eble, III
  • Optical systems and methods supporting diverse optical and computational functions
    Patent number: 10404908
    Abstract: An imaging system includes multiple diffractive optical gratings disposed over a two-dimensional array of photosensitive pixels. The different gratings present different patterns and features that are tailored to produce point-spread responses that emphasize different properties of an imaged scene. The different responses are captured by the pixels, and data captured from the responses can be used separately or together to analyze aspects of the scene. The imaging systems can include circuitry to analyze the image data, and to support modes that select between point-spread responses, selections of the pixels, and algorithms for analyzing image data.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: September 3, 2019
    Assignee: Rambus Inc.
    Inventors: David G. Stork, Patrick R. Gill, Evan L. Erickson, Mark D. Kellam, Alexander C. Schneider, Jay Endsley, Salman Kabir
  • Adjustable access energy and access latency memory system and devices
    Patent number: 10402110
    Abstract: Same sized blocks of data corresponding to a single read/write command are stored in the same memory array of a memory device, but using different formats. A first one of these formats spreads the data in the block across a larger number of memory subarrays (a.k.a., memory array tiles—MATs) than a second format. In this manner, the data blocks stored in the first format can be accessed with lower latency than the blocks stored in the second format because more data can be read from the array simultaneously. In addition, since the data stored in the second format is stored in fewer subarrays, it takes less energy to read a block stored in the second format. Thus, a system may elect, on a data block by data block basis, whether to conserve power or improve speed.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: September 3, 2019
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, John Eric Linstadt
  • Semiconductor memory systems with on-die data buffering
    Patent number: 10402352
    Abstract: A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: September 3, 2019
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Amir Amirkhany, Suresh Rajan, Mohammad Hekmat, Dinesh Patil
  • Using a stuttered clock signal to reduce self-induced voltage noise
    Patent number: 10401900
    Abstract: The disclosed embodiments relate to a technique that uses a modified timing signal to reduce self-induced voltage noise in a synchronous system. During a transient period associated with a deterministic event in the synchronous system, the technique uses a modified timing signal generated based on a normal timing signal as a timing signal for the synchronous system. Outside of the transient period, the technique uses the normal timing as the timing signal for the synchronous system. In some embodiments, the modified timing signal is generated by skipping a pattern of clock transitions in the normal timing signal.
    Type: Grant
    Filed: October 31, 2011
    Date of Patent: September 3, 2019
    Assignee: Rambus Inc.
    Inventors: Brian S. Leibowitz, Jared L. Zerbe
  • Receiver with time-varying threshold voltage
    Patent number: 10404236
    Abstract: A system for communicating information between circuits is described. A transmit circuit provides pulse-amplitude-modulation (PAM) signals via a communication channel to a receiver. A circuit in the receiver determines digital values from the received signals using a time-varying threshold voltage, which varies during the bit-time. This approach may compensate for inter-symbol interference (ISI) to increase the voltage and timing margins of the system.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: September 3, 2019
    Assignee: Rambus Inc.
    Inventors: Jared L. Zerbe, Brian S. Leibowitz, Qi Lin
  • Decision feedback equalizer
    Patent number: 10397028
    Abstract: A decision-feedback equalizer (DFE) samples an analog input signal against M references during the same symbol time to produce M speculative samples. Select logic in the DFE then decodes N bits resolved previously for previous symbol times to select one of the M speculative samples as the present resolved bit. The present resolved bit is then stored as the most recent previously resolved bit in preparation for the next symbol time. The select logic can be can be programmable to accommodate process, environmental, and systematic variations.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: August 27, 2019
    Assignee: Rambus Inc.
    Inventors: Brian S. Leibowitz, Jaeha Kim