Patents Assigned to Rambus
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Patent number: 10505769Abstract: A transmitter for providing channel equalization that includes a first driver and second driver having a high pass filter. The first driver generates a first output signal representing a digital input signal. The second driver generates a second output signal representing a high pass filtered version of the digital input signal. The first and second output signals are summed to provide a third output signal that is channel equalized for transmission over a channel.Type: GrantFiled: January 23, 2019Date of Patent: December 10, 2019Assignee: Rambus Inc.Inventor: John Wood Poulton
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Patent number: 10503201Abstract: A memory controller having a data receiver to sample data at a sample timing using a strobe signal, wherein the data and the strobe signal are sent by a memory device in connection with a read operation initiated by the memory controller, and a strobe receiver to receive the strobe signal, wherein a phase of the strobe signal has a drift relative to a reference by an amount. The memory controller further having a monitoring circuit to monitor the strobe signal and determine the amount of the drift, and an adjustment circuit to update the sample timing of the data receiver based on the amount of drift determined by the monitoring signal.Type: GrantFiled: June 7, 2017Date of Patent: December 10, 2019Assignee: Rambus Inc.Inventors: Scott C. Best, Abhijit M. Abhyankar, Kun-Yung Chang, Frank Lambrecht
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Patent number: 10505565Abstract: Memory controllers, devices and associated methods are disclosed. In one embodiment, a memory controller includes write circuitry to transmit write data to a memory device, the write circuitry includes a write error detection correction (EDC) encoder to generate first error information associated with the write data. Data bus inversion (DBI) circuitry conditionally inverts data bits associated with each of the write data words based on threshold criteria. Read circuitry receives read data from the memory device. The read circuitry includes a read EDC encoder to generate second error information associated with the received read data. Logic evaluates the first and second error information and conditionally reverse-inverts at least a portion of the read data based on the decoding.Type: GrantFiled: May 7, 2018Date of Patent: December 10, 2019Assignee: Rambus Inc.Inventors: Frederick A. Ware, John Eric Linstadt
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Patent number: 10495793Abstract: Image-sensing devices include odd-symmetry gratings that cast interference patterns over a photodetector array. Grating features offer considerable insensitivity to the wavelength of incident light, and also to the manufactured distance between the grating and the photodetector array. Photographs and other image information can be extracted from interference patterns captured by the photodetector array. Efficient extraction algorithms based on Fourier deconvolution introduce barrel distortion, which can be removed by resampling using correction functions.Type: GrantFiled: January 26, 2016Date of Patent: December 3, 2019Assignee: Rambus Inc.Inventor: Patrick R. Gill
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Patent number: 10497457Abstract: A method of operation in an integrated circuit (IC) memory device. The method includes refreshing a first group of storage rows in the IC memory device at a first refresh rate. A retention time for each of the rows is tested. The testing for a given row under test includes refreshing at a second refresh rate that is slower than the first refresh rate. The testing is interruptible based on an access request for data stored in the given row under test.Type: GrantFiled: June 16, 2017Date of Patent: December 3, 2019Assignee: Rambus Inc.Inventors: Ely Tsern, Frederick A Ware, Suresh Rajan, Thomas Vogelsang
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Patent number: 10496126Abstract: A memory system in which a timing drift that would occur in distribution of a first timing signal for data transport in a memory device is determined by measuring the actual phase delays occurring in a second timing signal that has a frequency lower than that of the first timing signal and is distributed in one or more circuits mimicking the drift characteristics of at least a portion of distribution of the first timing signal. The actual phase delays are determined in the memory device and provided to a memory controller so that the phases of the timing signals used for data transport may be adjusted based on the determined timing drift.Type: GrantFiled: December 27, 2016Date of Patent: December 3, 2019Assignee: Rambus Inc.Inventors: Jun Kim, Pak Shing Chau, Wayne S. Richardson
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Patent number: 10489611Abstract: A side-channel attack resistant circuit topology for performing logic functions. This topology includes combinatorial logic to perform the at least one logic function. A logic input selector alternately supplies, in response to a first timing reference signal, an input to the combinatorial logic with noise generating input values and valid input values. A first latch input selector alternately supplies, in response to the first timing reference signal, a first memory element input with noise generating input values and valid logic output values. The valid logic output values are received from the combinatorial logic. A first memory element latches the valid logic output values in response to a second timing reference signal.Type: GrantFiled: August 24, 2016Date of Patent: November 26, 2019Assignee: Rambus Inc.Inventors: Roberto Rivoir, Elke De Mulder, Jean-Michel Cioranesco
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Patent number: 10481973Abstract: A memory module is disclosed. The memory module includes a substrate, and respective first, second and third memory devices. The first memory device is of a first type disposed on the substrate and has addressable storage locations. The second memory device is also of the first type, and includes storage cells dedicated to store failure address information associated with defective storage locations in the first memory device. The third memory device is of the first type and includes storage cells dedicated to substitute as storage locations for the defective storage locations.Type: GrantFiled: February 27, 2018Date of Patent: November 19, 2019Assignee: Rambus Inc.Inventors: Frederick A. Ware, Brent S. Haukness, John Eric Linstadt, Scott C. Best
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Patent number: 10475505Abstract: A stacked semiconductor device is disclosed that includes a plurality of semiconductor dies. Each die has oppositely disposed first and second surfaces, with pads formed on each of the surfaces. A plurality of through-vias connect respective pads on the first surface to respective pads on the second surface. The through-vias include a first group of through-vias coupled to respective I/O circuitry on the semiconductor die and a second group of through-vias not coupled to I/O circuitry on the semiconductor die. The plurality of semiconductor dies are stacked such that the first group of through-vias in a first one of the plurality of semiconductor dies are aligned with respective ones of at least a portion of the second group of through-vias in a second one of the plurality of semiconductor dies.Type: GrantFiled: January 16, 2018Date of Patent: November 12, 2019Assignee: Rambus Inc.Inventor: Frederick A. Ware
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Patent number: 10468544Abstract: A memory controller comprises a command interface to transmit a memory command to a plurality of memory devices associated with the memory controller. The memory controller also comprises an acknowledgement interface to receive an acknowledgment status packet from the plurality of memory devices over a shared acknowledgement link coupled between the memory controller and the plurality of memory devices, the acknowledgement status packet indicating whether the command was received by the plurality of memory devices. In addition, the memory controller comprises a memory controller core to decode the acknowledgment status packet to identify a portion of the acknowledgement status packet corresponding to each of the plurality of memory devices.Type: GrantFiled: December 5, 2016Date of Patent: November 5, 2019Assignee: Rambus Inc.Inventors: Yohan Frans, Simon Li, Eric Linstadt, Jun Kim
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Patent number: 10466289Abstract: An integrated circuit capable of on-chip jitter tolerance measurement includes a jitter generator circuit to produce a controlled amount of jitter that is injected into at least one clock signal, and a receive circuit to sample an input signal according to the at least one clock signal. The sampled data values output from the receiver are used to evaluate the integrated circuit's jitter tolerance.Type: GrantFiled: September 8, 2017Date of Patent: November 5, 2019Assignee: Rambus Inc.Inventors: Hae-Chang Lee, Jaeha Kim, Brian Leibowitz
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Patent number: 10467157Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, a memory controller is disclosed. The memory controller includes write queue logic that has first storage to temporarily store signal components of a write operation. The signal components include an address and write data. A transfer interface issues the signal components of the write operation to a bank of a storage class memory (SCM) device and generates a time value. The time value represents a minimum time interval after which a subsequent write operation can be issued to the bank. The write queue logic includes an issue queue to store the address and the time value for a duration corresponding to the time value.Type: GrantFiled: December 12, 2016Date of Patent: November 5, 2019Assignee: Rambus Inc.Inventors: Frederick A. Ware, Brent Haukness
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Patent number: 10459660Abstract: A memory module with multiple memory devices includes a buffer system that manages communication between a memory controller and the memory devices. The memory module additionally includes a command input port to receive command and address signals from a controller and, also in support of capacity extensions, a command relay circuit coupled to the command port to convey the commands and addresses from the memory module to another module or modules. Relaying commands and addresses introduces a delay, and the buffer system that manages communication between the memory controller and the memory devices can be configured to time data communication to account for that delay.Type: GrantFiled: November 4, 2015Date of Patent: October 29, 2019Assignee: Rambus Inc.Inventors: Frederick A. Ware, Scott C. Best
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Patent number: 10461969Abstract: In a PAM-N receiver, sampler reference levels, DC offset and AFE gain may be jointly adapted to achieve optimal or near-optimal boundaries for the symbol decisions of the PAM-N signal. For reference level adaptation, the hamming distances between two consecutive data samples and their in-between edge sample are evaluated. Reference levels for symbol decisions are adjusted accordingly such that on a data transition, an edge sample has on average, equal hamming distance to its adjacent data samples. DC offset may be compensated to ensure detectable data transitions for reference level adaptation. AFE gains may be jointly adapted with sampler reference levels such that the difference between a reference level and a pre-determined target voltage is minimized.Type: GrantFiled: April 19, 2018Date of Patent: October 29, 2019Assignee: Rambus Inc.Inventor: Nanyan Wang
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Patent number: 10452478Abstract: A memory component internally generates and stores the check bits of error detect and correct code (EDC). In a first mode, during a read transaction, the check bits are sent to the memory controller along with the data on the data mask (DM) signal lines. In a second mode, an unmasked write transaction is defined where the check bits are sent to the memory component on the data mask signal lines. In a third mode, a masked write transaction is defined where at least a portion of the check bits are sent from the memory controller on the data signal lines coincident with an asserted data mask signal line. By sending the check bits along with the data, the EDC code can be used to detect and correct errors that occur between the memory component and the memory controller.Type: GrantFiled: October 26, 2017Date of Patent: October 22, 2019Assignee: Rambus Inc.Inventors: Frederick A. Ware, Brent S. Haukness, Lawrence Lai
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Patent number: 10453500Abstract: A packaged semiconductor device includes a data pin, a first memory die, and a second memory die stacked with the first memory die. The first memory die includes a first data interface coupled to the data pin and a first memory core having a plurality of banks. The second memory die includes a second memory core having a plurality of banks. A respective bank of the first memory core and a respective bank of the second memory core perform parallel row access operations in response to a first command signal and parallel column access operations in response to a second command signal. The first data interface of the first die provides aggregated data from the parallel column access operations in the first and second die to the data pin.Type: GrantFiled: February 27, 2018Date of Patent: October 22, 2019Assignee: Rambus Inc.Inventor: Yohan Frans
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Patent number: 10455698Abstract: The embodiments described herein describe technologies for memory systems. One implementation of a memory system includes a motherboard substrate with multiple module sockets, at least one of which is populated with a memory module. A first set of data lines is disposed on the motherboard substrate and coupled to the module sockets. The first set of data lines includes a first subset of point-to-point data lines coupled between a memory controller and a first socket and a second subset of point-to-point data lines coupled between the memory controller and a second socket. A second set of data lines is disposed on the motherboard substrate and coupled between the first socket and the second socket. The first and second sets of data lines can make up a memory channel.Type: GrantFiled: December 3, 2018Date of Patent: October 22, 2019Assignee: Rambus, Inc.Inventors: Frederick A. Ware, Suresh Rajan
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Patent number: 10453517Abstract: The embodiments described herein describe technologies for using the memory modules in different modes of operation, such as in a standard multi-drop mode or as in a dynamic point-to-point (DPP) mode (also referred to herein as an enhanced mode). The memory modules can also be inserted in the sockets of the memory system in different configurations.Type: GrantFiled: April 10, 2017Date of Patent: October 22, 2019Assignee: Rambus Inc.Inventors: Frederick A. Ware, Suresh Rajan, Scott C. Best
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Patent number: 10447270Abstract: A combinational logic circuit includes input circuitry to receive a first input signal that transitions between upper and lower voltages of a first voltage domain, and to generate, in response to the transitions of the first input signal, a first localized signal that transitions between upper and lower voltages of a second voltage domain. The combinational logic circuit additionally includes output circuitry to generate a first output signal that transitions between the upper and lower supply voltages of the first voltage domain based at least in part on the transitions of the first localized signal.Type: GrantFiled: October 1, 2018Date of Patent: October 15, 2019Assignee: Rambus Inc.Inventors: Frederick A. Ware, John Eric Linstadt
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Patent number: 10447427Abstract: A receiver frontend having a high-frequency AC-coupled path in parallel to a low-frequency feed-forward path for baseline correction. The low-frequency path blocks the DC common-mode voltage of the input differential signal pair, but passes low-frequency differential signal components (e.g., long strings of a single value, or disparities in the number of 1's and 0's over a long period of time.) The low-frequency path can include a passive network for level shifting and extending the range of acceptable common-mode input voltages. The low-frequency path can also include a differential (e.g., transconductance) amplifier to isolate the common-mode input voltage from the output of the baseline wander correction circuit.Type: GrantFiled: October 12, 2018Date of Patent: October 15, 2019Assignee: Rambus Inc.Inventor: Reza Navid