Patents Assigned to Rambus
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Patent number: 10135647Abstract: A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.Type: GrantFiled: January 23, 2018Date of Patent: November 20, 2018Assignee: Rambus Inc.Inventors: Jared L. Zerbe, Fariborz Assaderaghi, Brian S. Leibowitz, Hae-Chang Lee, Jihong Ren, Qi Lin
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Patent number: 10136090Abstract: An image sensor architecture with multi-bit sampling is implemented within an image sensor system. A pixel signal produced in response to light incident upon a photosensitive element is converted to a multiple-bit digital value representative of the pixel signal. If the pixel signal exceeds a sampling threshold, the photosensitive element is reset. During an image capture period, digital values associated with pixel signals that exceed a sampling threshold are accumulated into image data.Type: GrantFiled: March 14, 2014Date of Patent: November 20, 2018Assignee: Rambus Inc.Inventors: Thomas Vogelsang, Michael Guidash, Song Xue, Maxim Smirnov, Craig M. Smith, Jay Endsley, James E. Harris
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Patent number: 10135427Abstract: A system for communicating information between circuits is described. A transmit circuit provides pulse-amplitude-modulation (PAM) signals via a communication channel to a receiver. A circuit in the receiver determines digital values from the received signals using a time-varying threshold voltage, which varies during the bit-time. This approach may compensate for inter-symbol interference (ISI) to increase the voltage and timing margins of the system.Type: GrantFiled: December 1, 2017Date of Patent: November 20, 2018Assignee: Rambus Inc.Inventors: Jared L. Zerbe, Brian S. Leibowitz, Qi Lin
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Patent number: 10133693Abstract: A memory system includes a memory controller coupled to multiple memory devices. Each memory device includes an oscillator that generates an internal reference signal that oscillates at a frequency that is a function of physical device structures within the memory device. The frequencies of the internal reference signals are thus device specific. Each memory device develops a shared reference signal from its internal reference signal and communicates the shared reference signal to the common memory controller. The memory controller uses the shared reference signals to recover device-specific frequency information from each memory device, and then communicates with each memory device at a frequency compatible with the corresponding internal reference signal.Type: GrantFiled: November 30, 2017Date of Patent: November 20, 2018Assignee: Rambus Inc.Inventors: Scott C. Best, Ian Shaeffer
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Patent number: 10129015Abstract: A receiver with clock phase calibration. A first sampling circuit generates first digital data based on an input signal, a sampling phase of the first sampling circuit controlled by a first clock signal. A second sampling circuit generates second digital data based on the input signal, a sampling phase of the second sampling circuit controlled by a second clock signal. Circuitry within the receiver calibrates the clocks in different stages. During a first calibration stage, a phase of the second clock signal is adjusted while the first digital data is selected for generating the output data. During a second calibration stage, a phase of the first clock signal is adjusted while the first digital data is selected for the output data path.Type: GrantFiled: July 25, 2017Date of Patent: November 13, 2018Assignee: Rambus Inc.Inventors: Marko Aleksić, Simon Li, Roxanne Vu
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Patent number: 10120600Abstract: The present invention is directed to memory systems. More specifically, embodiments of the present invention provide a memory system with a volatile memory, a persistent memory, and a controller. In a save operation, the controller copies contents of the volatile memory to the persistent memory as data units with their corresponding descriptor fields, where the descriptor fields include address information. In a restore operation, the controller copies data units from the persistent memory to their corresponding locations based on addresses stored at descriptor fields. There are other embodiments as well.Type: GrantFiled: October 10, 2017Date of Patent: November 6, 2018Assignee: Rambus Inc.Inventors: Aws Shallal, Collins Williams, Dan Kunkel, William Wolf
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Patent number: 10114073Abstract: Systems and methods of testing integrated circuits are disclosed. A system may include a data compression component to compress data received from an integrated circuit under test at a first clock frequency, to generate compressed data. The system may also include a data output component, operatively coupled to the data compression component, to convey the compressed data to automated testing equipment at a second clock frequency.Type: GrantFiled: August 17, 2015Date of Patent: October 30, 2018Assignee: Rambus Inc.Inventor: Adrian E. Ong
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Patent number: 10108488Abstract: A memory system includes a memory module that supports error detection and correction (EDC) in a manner that relieves a memory controller or processor of some or all of the computational burden associated with EDC. Individual EDC components perform EDC functions on subsets of the data, and share data between themselves using relatively short, fast interconnections.Type: GrantFiled: September 1, 2016Date of Patent: October 23, 2018Assignee: Rambus Inc.Inventors: Frederick A. Ware, Scott C. Best
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Patent number: 10109324Abstract: A memory module uses dynamic data buffers for providing extended capacity for computing systems. The memory module comprises an external interface having a first set of data pins and a second set of data pins. The memory module includes a first set of memory chips and a second set of memory chips. The memory module includes a first registering clock driver to control the first set of memory chips and a second registering clock driver to control the second set of memory chips. The memory module further includes a first data buffer to connect the first set of memory chips to the first set of data pins and a second data buffer to connect the second set of memory chips to the second set of data pins.Type: GrantFiled: January 26, 2018Date of Patent: October 23, 2018Assignee: Rambus Inc.Inventors: Thomas J. Giovannini, John Eric Linstadt
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Patent number: 10108246Abstract: The disclosed embodiments relate to a system that supports dynamic bursts to facilitate frequency-agile communication between a memory controller and a memory device. During operation, the system monitors a reference clock signal received at an interface between the memory device and the memory controller. Upon detecting a frequency change in the reference clock signal from a fullrate to a subrate, the interface operates in a burst mode, wherein data is communicated through bursts separated by intervening low-power intervals during which portions of the interface are powered down.Type: GrantFiled: December 23, 2016Date of Patent: October 23, 2018Assignee: Rambus Inc.Inventors: Jared L. Zerbe, Brian Hing-Kit Tsang, Barry William Daly
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Patent number: 10103907Abstract: A signaling circuit having a selectable-tap equalizer. The signaling circuit includes a buffer, a select circuit and an equalizing circuit. The buffer is used to store a plurality of data values that correspond to data signals transmitted on a signaling path during a first time interval. The select circuit is coupled to the buffer to select a subset of data values from the plurality of data values according to a select value. The equalizing circuit is coupled to receive the subset of data values from the select circuit and is adapted to adjust, according to the subset of data values, a signal level that corresponds to a data signal transmitted on the signaling path during a second time interval.Type: GrantFiled: September 25, 2017Date of Patent: October 16, 2018Assignee: Rambus Inc.Inventors: Jared L. Zerbe, Vladimir M. Stojanovic, Fred F. Chen
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Patent number: 10104318Abstract: A pixel array within an integrated-circuit image sensor is exposed to light representative of a scene during a first frame interval and then oversampled a first number of times within the first frame interval to generate a corresponding first number of frames of image data from which a first output image may be constructed. One or more of the first number of frames of image data are evaluated to determine whether a range of luminances in the scene warrants adjustment of an oversampling factor from the first number to a second number, if so, the oversampling factor is adjusted such that the pixel array is oversampled the second number of times within a second frame interval to generate a corresponding second number of frames of image data from which a second output image may be constructed.Type: GrantFiled: December 3, 2014Date of Patent: October 16, 2018Assignee: Rambus Inc.Inventors: Craig M. Smith, Frank Armstrong, Jay Endsley, Thomas Vogelsang, James E. Harris, John Ladd, Michael Guidash
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Patent number: 10102887Abstract: A lateral transfer path within an adjustable-width signaling interface of an integrated circuit component is formed by a chain of logic segments that may be intercoupled in different groups to effect the lateral data transfer required in different interface width configurations, avoiding the need for a dedicated transfer path per width configuration and thereby substantially reducing number of interconnects (and thus the area) required to implement the lateral transfer structure.Type: GrantFiled: October 25, 2017Date of Patent: October 16, 2018Assignee: Rambus Inc.Inventor: Frederick A. Ware
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Patent number: 10102081Abstract: The present invention is directed to computer storage systems and methods thereof. More specifically, embodiments of the present invention provide an isolated storage control system that includes both a non-volatile memory and a volatile memory. The non-volatile memory comprises a data area and a metadata area. In power failure or similar situations, content of the volatile memory is copied to the data area of the non-volatile memory, and various system parameters are stored at the metadata area. When the system restores its operation, the information at the metadata area is processed, and the content stored at the data area of the non-volatile memory is copied to the volatile memory. There are other embodiments as well.Type: GrantFiled: January 9, 2017Date of Patent: October 16, 2018Assignee: Rambus Inc.Inventors: Shih-ho Wu, Christopher Haywood
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Patent number: 10095565Abstract: A memory system includes a link having at least one signal line and a controller. The controller includes at least one transmitter coupled to the link to transmit first data, and a first error protection generator coupled to the transmitter. The first error protection generator dynamically adds an error detection code to at least a portion of the first data. At least one receiver is coupled to the link to receive second data. A first error detection logic determines if the second data received by the controller contains at least one error and, if an error is detected, asserts a first error condition. The system includes a memory device having at least one memory device transmitter coupled to the link to transmit the second data. A second error protection generator coupled to the memory device transmitter dynamically adds an error detection code to at least a portion of the second data.Type: GrantFiled: September 15, 2015Date of Patent: October 9, 2018Assignee: Rambus Inc.Inventors: Ely K. Tsern, Mark A. Horowitz, Frederick A. Ware
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Patent number: 10091036Abstract: Methods and apparatuses for direct sequence detection can receive an input signal over a communication channel. Next, the input signal can be sampled based on a clock signal to obtain a sampled voltage. A set of reference voltages can be generated based on a main cursor, a set of pre-cursors, and a set of post-cursors associated with the communication channel. Each generated reference voltage in the set of reference voltages can correspond to a particular sequence of symbols. A sequence corresponding to the sampled voltage can be selected based on comparing the sampled voltage with the set of reference voltages.Type: GrantFiled: June 15, 2017Date of Patent: October 2, 2018Assignee: Rambus Inc.Inventors: Masum Hossain, Maruf H. Mohammad
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Patent number: 10089256Abstract: A transmitter is coupled to a command and address (CA) bus. The transmitter is configurable with dual-mode support to send commands over the CA bus in a first swing mode and a second swing mode. The transmitter is configurable to send a first command over the CA bus via the pins while in the first swing mode, initiate calibration of the master device to send commands over the CA bus in the second swing mode, and to send a second command over the CA bus via the pins while in the second swing mode.Type: GrantFiled: June 7, 2017Date of Patent: October 2, 2018Assignee: Rambus Inc.Inventors: Pravin Kumar Venkatesan, Liji Gopalakrishnan, Kashinath Prabhu, Makarand Shirasgaonkar
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Patent number: 10074417Abstract: A memory module with multiple memory devices includes a buffer system that manages communication between a memory controller and the memory devices. Each memory device supports an access mode and a low-power mode, the latter used to save power for devices that are not immediately needed. The module provides granular power management using a chip-select decoder that decodes chip-select signals from the memory controller into power-state signals that determine which of the memory devices are in which of the modes. Devices can thus be brought out of the low-power mode in relatively small numbers, as needed, to limit power consumption.Type: GrantFiled: November 4, 2015Date of Patent: September 11, 2018Assignee: Rambus Inc.Inventors: Frederick A. Ware, James E. Harris
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Patent number: 10070084Abstract: A pixel within a pixel array of an integrated-circuit image sensor outputs an analog signal representative of accumulated photocharge. First and second analog-to-digital conversions of the analog signal are initiated while the pixel is outputting the analog signal, the first analog-to-digital conversion corresponding to a low-light range of photocharge accumulation within the pixel and the second analog-to-digital conversion corresponding to a brighter-light range of photocharge accumulation within the pixel.Type: GrantFiled: January 6, 2016Date of Patent: September 4, 2018Assignee: Rambus Inc.Inventors: Michael Guidash, Jay Endsley, John Ladd, Thomas Vogelsang, Craig M. Smith
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Patent number: 10067519Abstract: An integrated circuit includes a voltage regulator to supply a regulated voltage and a data output that couples to an unterminated transmission line. The circuit draws a variable amount of power from the voltage regulator according to the data. The voltage regulator includes a first current generation circuit to provide a data transition-dependent current.Type: GrantFiled: June 17, 2017Date of Patent: September 4, 2018Assignee: Rambus Inc.Inventors: Brian S. Leibowitz, Michael D. Bucher, Lei Luo, Chaofeng Charlie Huang, Amir Amirkhany, Huy M. Nguyen, Hsuan-Jung (Bruce) Su, John Wilson