Abstract: A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.

Abstract: An extended-height DIMM for use in a memory system having slots designed to receive DIMMs that comply with a JEDEC standard that specifies a maximum height for the DIMM and a maximum number of devices allowed to reside on the DIMM. The DIMM comprises a PCB having an edge connector designed to mate with a memory system slot and a height which is greater than the maximum height specified in the applicable standard, a plurality of memory devices which exceeds the maximum number of devices specified in the applicable standard, and a memory buffer, or a register control device and data buffers, which operates as an interface between a host controller's data and command/address busses and the memory devices. This arrangement enables the extended-height DIMM to provide greater memory capacity than would a DIMM which complies with the maximum height and maximum number of devices limits.

Abstract: A memory controller receives data and phase-providing signals from a memory device. The phase-providing signal is not a clock signal, but is used by the memory controller to phase align a local data-sampling signal with the incoming data. The memory controller samples the data signal with the data-sampling signal. The memory controller can perform maintenance operations to update the phase relationship between the phase-providing and data-sampling signals.

Abstract: A memory controller component includes transmit circuitry and adjusting circuitry. The transmit circuitry transmits a clock signal and write data to a DRAM, the write data to be sampled by the DRAM using a timing signal. The adjusting circuitry adjusts transmit timing of the write data and of the timing signal such that an edge transition of the timing signal is aligned with an edge transition of the clock signal at the DRAM.

Abstract: A signaling system includes a pre-emphasizing transmitter and an equalizing receiver coupled to one another via a high-speed signal path. The receiver measures the quality of data conveyed from the transmitter. A controller uses this information and other information to adaptively establish appropriate transmit pre-emphasis and receive equalization settings, e.g. to select the lowest power setting for which the signaling system provides some minimum communication bandwidth without exceeding a desired bit-error rate.

Abstract: A memory controller encrypts contents of a page frame based at least in part on a frame key associated with the page frame. The memory controller generates a first encrypted version of the frame key based at least in part on a first process key associated with a first process, wherein the first encrypted version of the frame key is stored in a first memory table associated with the first process. The memory controller generates a second encrypted version of the frame key based at least in part on a second process key associated with a second process, wherein the second encrypted version of the frame key is stored in a second memory table associated with the second process, the first process and the second process sharing access to the page frame using the first encrypted version of the frame key and the second encrypted version of the frame key, respectively.

Abstract: A memory device (100) includes an extra column (114) of repair memory tiles. These repair memory tiles are accessed at the same time, and in the same manner as the main array of memory tiles. The output of the repair column is substituted for the output of a column of the main array (112). The main array column that is substituted is determined by tags (121) stored externally to the memory device. The external tags are queried with a partial address of the access. If the address of the access corresponds to an address in the external tags, the tag information is supplied to the memory device. The tag information determines which column in the main array is replaced by the output of the repair column. Since each column of the main array supplies one bit during the access, the repair column enables cell-by-cell replacement of main array cells.

Abstract: A method for calibrating a communication channel coupling first and second components includes transmitting a data signal from the first component to the second component on the communication channel, and sensing a characteristic, such as phase, of the data signal on the second component. Information about the sensed characteristic is fed back to the first component using an auxiliary channel. An adjustable parameter, such as phase, for the transmitter is adjusted on the first component in response to the information. Also, a characteristic of a data signal received from the transmitter on the second component is sensed and used to adjust an adjustable parameter for the receiver on the first component.

Abstract: A memory device or module selects between alternative command ports. Memory systems with memory modules incorporating such memory devices support point-to-point connectivity and efficient interconnect usage for different numbers of modules. The memory devices and modules can be of programmable data widths. Devices on the same module can be configured select different command ports to facilitate memory threading. Modules can likewise be configured to select different command ports for the same purpose.

Abstract: In a first clock frequency multiplier, multiple injection-locked oscillators (ILOs) having spectrally-staggered lock ranges are operated in parallel to effect a collective input frequency range substantially wider than that of a solitary ILO. After each input frequency change, the ILO output clocks may be evaluated according to one or more qualifying criteria to select one of the ILOs as the final clock source. In a second clock frequency multiplier, a flexible-injection-rate injection-locked oscillator locks to super-harmonic, sub-harmonic or at-frequency injection pulses, seamlessly transitioning between the different injection pulse rates to enable a broad input frequency range. The frequency multiplication factor effected by the first and/or second clock frequency multipliers in response to an input clock is determined on the fly and then compared with a programmed (desired) multiplication factor to select between different frequency-divided instances of the frequency-multiplied clock.

Abstract: An integrated circuit (IC) memory controller is disclosed. The memory controller includes a receiver to receive a strobe signal and provide an internal strobe signal. An adjustable delay circuit delays an enable signal to generate a delayed enable signal. A gate circuit generates a gated strobe signal using the delayed enable signal that masks transitions of the internal strobe signal that occur prior to a valid region of the internal strobe signal. A sample circuit samples data using the gated strobe signal.

Abstract: A phase-locked loop circuit comprises a multi-phase oscillator having a plurality of coupled oscillators. A calibration module detects mismatches between frequency characteristics of the different oscillators in the phase-locked loop circuit during a calibration process. The calibration module then calibrates the various oscillators to compensate for the detected mismatch. Once calibrated, the phase-locked loop circuit can operate with little or no performance degradation despite the mismatch in frequency characteristics between the different oscillators.

Abstract: A memory component includes a memory core comprising dynamic random access memory (DRAM) storage cells and a first circuit to receive external commands. The external commands include a read command that specifies transmitting data accessed from the memory core. The memory component also includes a second circuit to transmit data onto an external bus in response to a read command and pattern register circuitry operable during calibration to provide at least a first data pattern and a second data pattern. During the calibration, a selected one of the first data pattern and the second data pattern is transmitted by the second circuit onto the external bus in response to a read command received during the calibration. Further, at least one of the first and second data patterns is written to the pattern register circuitry in response to a write command received during the calibration.

Abstract: A memory device is disclosed that includes a row of storage locations that form plural columns. The plural columns include data columns to store data and a tag column to store tag information associated with error locations in the data columns. Each data column is associated with an error correction location including an error code bit location. Logic retrieves and stores the tag information associated with the row in response to activation of the row. A bit error in an accessed data column is repaired by a spare bit location based on the tag information.

Abstract: A single-ended receiver is coupled to an input-output (I/O) pin of a command and address (CA) bus. The receiver is configurable with dual-mode I/O support to operate the CA bus in a low-swing mode and a high-swing mode. The receiver is configurable to receive a first command on the I/O pin while in the high-swing mode, initiate calibration of the slave device to operate in the low-swing mode in response to the first command, switch the slave device to operate in the low-swing mode while the CA bus remains active, and to receive a second command on the I/O pin while in the low-swing mode.

Abstract: A clock and data recovery circuit (CDR) includes a digitally controlled oscillator (DCO). A data sampler is coupled to receive a clock signal from the DCO. A deserializer includes an input coupled to an output of the data sampler. A first phase detector is coupled between a first output of the deserializer and a first input of the DCO. A second phase detector is coupled to a second output of the deserializer. An accumulator is coupled between an output of the second phase detector and a second input of the DCO. A frequency lock detection block is coupled to an output of the accumulator. An eye monitor is coupled to an input of the data sampler. The first phase detector controls a delay of the DCO and the accumulator controls a frequency of the DCO. An edge mute signal is coupled to the deserializer.

Abstract: The disclosed embodiments relate to a system that supports dynamic bursts to facilitate frequency-agile communication between a memory controller and a memory device. During operation, the system monitors a reference clock signal received at an interface between the memory device and the memory controller. Upon detecting a frequency change in the reference clock signal from a fullrate to a subrate, the interface operates in a burst mode, wherein data is communicated through bursts separated by intervening low-power intervals during which portions of the interface are powered down.

Abstract: Methods and apparatuses featuring a multiplying injection-locked oscillator are described. Some embodiments include a pulse-generator-and-injector and one or more injection-locked oscillators. The outputs of the pulse-generator-and-injector can be injected into corresponding injection points of an injection-locked oscillator. In embodiments that include multiple injection-locked oscillators, the outputs of each injection-locked oscillator can be injected into the corresponding injection points of the next injection-locked oscillator. Some embodiments reduce deterministic jitter by dynamically modifying the loop length of an injection-locked oscillator, and/or by using a duty cycle corrector, and/or by multiplexing/blending the outputs from multiple delay elements of an injection-locked oscillator.

Abstract: Optical elements with small increments in average density are formed in a substrate by laser micromachining using a variable aperture and a pattern mask set of pattern masks each having of shape-defining elements whose density differs among the pattern masks in first density increments. A laser light beam passes through a combined mask formed by the variable aperture and one pattern mask selected from the pattern mask set. The variable aperture controls beam size and the pattern mask spatially modulates its intensity. A focusing element focuses light from the combined mask on a small averaging region of the substrate. Different combinations of the size of the aperture mask and the selected pattern mask are used in combination at respective averaging regions of the substrate. The resulting average densities of the optical elements vary among the averaging regions in increments that are small compared to the first density increments.

Abstract: A memory controller having a data receiver to sample data at a sample timing using a strobe signal, wherein the data and the strobe signal are sent by a memory device in connection with a read operation initiated by the memory controller, and a strobe receiver to receive the strobe signal, wherein a phase of the strobe signal has a drift relative to a reference by an amount. The memory controller further having a monitoring circuit to monitor the strobe signal and determine the amount of the drift, and an adjustment circuit to update the sample timing of the data receiver based on the amount of drift determined by the monitoring signal.