Patents Assigned to Rambus
  • Lighting assembly with edge-lit light guide and structured cover
    Patent number: 9645301
    Abstract: A cover element for use in a lighting assembly that includes an edge-lit light guide. The cover element includes a first major surface through which light output by the light guide enters the cover element, the light including light propagating at high angles relative to normal to the first major surface of the cover element. The cover element also includes a second major surface opposed to the first major surface and having optical elements that each have plural surfaces arranged relative one another so that the optical element redirects high angle light incident on any one of the surfaces of the optical element and travelling in a direction with any vector component orthogonal to the normal to have a reduced angle in the normal direction as the light exits the cover element through the optical element.
    Type: Grant
    Filed: November 7, 2014
    Date of Patent: May 9, 2017
    Assignee: Rambus Delaware LLC
    Inventor: Dane A. Sahlhoff
  • Article of manufacture with micro-features of differing surface roughness
    Patent number: 9638853
    Abstract: An article of manufacture includes first and second micro-features of well-defined shape. In some embodiments, the article of manufacture is a light guide or redirecting film and the second micro-features are micro-optical elements configured to disrupt a specular optical path that includes the second micro-optical element. In other embodiments, the article of manufacture is a patterning tool for use in making an optical substrate. Embodiments of the optical substrate are formed by injection molding or embossing using the patterning tool.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: May 2, 2017
    Assignee: Rambus Delaware LLC
    Inventors: Kurt R. Starkey, Robert M. Ezell, Fumitomo Hide
  • Expandable asymmetric-channel memory system
    Patent number: 9632956
    Abstract: An expandable memory system that enables a fixed signaling bandwidth to be configurably re-allocated among dedicated memory channels. Memory channels having progressively reduced widths are dedicated to respective memory sockets, thus enabling point-to-point signaling with respect to each memory socket without signal-compromising traversal of unloaded sockets or costly replication of a full-width memory channel for each socket.
    Type: Grant
    Filed: October 2, 2015
    Date of Patent: April 25, 2017
    Assignee: Rambus Inc.
    Inventors: Ian Shaeffer, Arun Vaidyanath, Sanku Mukherjee
  • Light emitting panel assemblies
    Patent number: 9625633
    Abstract: An optical assembly comprises light sources and a light emitting panel member having an input edge to which each of the light sources is optically coupled at a different location along the input edge. Different sets of individual optical deformities on or in at least one of the sides of the panel member each have at least one surface that is shaped or oriented to extract light propagating in the same direction through the panel member in different directions for viewing from different angles through one of the sides of the panel member.
    Type: Grant
    Filed: July 8, 2014
    Date of Patent: April 18, 2017
    Assignee: Rambus Delaware LLC
    Inventors: Timothy A. McCollum, Jeffery R. Parker, Robert M. Ezell
  • Communication channel calibration for drift conditions
    Patent number: 9628257
    Abstract: A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component.
    Type: Grant
    Filed: November 4, 2015
    Date of Patent: April 18, 2017
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Richard E. Perego, Craig E. Hampel
  • Deserialized Dual-Loop Clock Radio and Data Recovery Circuit
    Publication number: 20170093558
    Abstract: A clock and data recovery circuit (CDR) includes a digitally controlled oscillator (DCO). A data sampler is coupled to receive a clock signal from the DCO. A deserializer includes an input coupled to an output of the data sampler. A first phase detector is coupled between a first output of the deserializer and a first input of the DCO. A second phase detector is coupled to a second output of the deserializer. An accumulator is coupled between an output of the second phase detector and a second input of the DCO. A frequency lock detection block is coupled to an output of the accumulator. An eye monitor is coupled to an input of the data sampler. The first phase detector controls a delay of the DCO and the accumulator controls a frequency of the DCO. An edge mute signal is coupled to the deserializer.
    Type: Application
    Filed: September 30, 2015
    Publication date: March 30, 2017
    Applicant: Rambus Inc.
    Inventors: Mehrdad Ramezani, David J. Cassan, Christopher D. Holdenried, Sang-Wook Paul Park, Marcus van Ierssel
  • Clock and data recovery having shared clock generator
    Patent number: 9577816
    Abstract: This disclosure provides a clock recovery circuit for a multi-lane communication system. Local clocks are recovered from the input signals using respective local CDR circuits, and associated CDR error signals are aggregated or otherwise combined. A global recovered clock for shared use by the local CDR circuits is generated at a controllable oscillation frequency as a function of a combination of the error signals from the plurality of receivers. A voltage- or current-controlled delay line can also be used to phase adjust the global recovered clock to mitigate band-limited, lane-correlated, high frequency jitter.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: February 21, 2017
    Assignee: Rambus Inc.
    Inventors: Masum Hossain, Brian Leibowitz, Jihong Ren
  • Error correction in a memory device
    Patent number: 9575835
    Abstract: A dynamic random access memory (DRAM) array is configured for selective repair and error correction of a subset of the array. Error-correcting code (ECC) is provided to a selected subset of the array to protect a row or partial row of memory cells where one or more weak memory cells are detected. By adding a sense amplifier stripe to the edge of the memory array, the adjacent edge segment of the array is employed to store ECC information associated with the protected subsets of the array. Bit replacement is also applied to defective memory cells. By implementing ECC selectively rather than to the entire array, integrity of the memory array is maintained at minimal cost to the array in terms of area and energy consumption.
    Type: Grant
    Filed: April 21, 2015
    Date of Patent: February 21, 2017
    Assignee: Rambus Inc.
    Inventors: Thomas Vogelsang, Suresh N. Rajan, Ian P. Shaeffer, Frederick A. Ware, Wayne F. Ellis
  • Protocol for refresh between a memory controller and a memory device
    Patent number: 9570145
    Abstract: The present embodiments provide a system that supports self-refreshing operations in a memory device. During operation, the system transitions the memory device from an auto-refresh state, wherein a memory controller controls refreshing operations for the memory device, to a self-refresh state, wherein the memory device controls the refreshing operations. While the memory device is in the self-refresh state, the system sends progress information for the refreshing operations from the memory device to the memory controller. Next, upon returning from the self-refresh state to the auto-refresh state, the system uses the progress information received from the memory device to control the sequencing of subsequent operations by the memory controller.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: February 14, 2017
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Brent Haukness
  • Memory refresh method and devices
    Patent number: 9570144
    Abstract: The present disclosure describes DRAM architectures and refresh controllers that allow for scheduling of an opportunistic refresh of a DRAM device concurrently with normal row activate command directed toward the DRAM device. Each activate command affords an “opportunity” to refresh another independent row (i.e., a wordline) within a memory device with no scheduling conflict.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: February 14, 2017
    Assignee: Rambus Inc.
    Inventors: Richard Perego, Thomas Vogelsang, John Brooks
  • Electronic circuits using coupled multi-inductors
    Patent number: 9571034
    Abstract: Coupled multi-inductors and their applications. An apparatus includes several circuit stages. Each circuit stage includes an inductive element that overlaps with the inductive elements of its adjacent circuit stages, forming a loop of coupled circuit stages. The apparatus may be, for example, a multi-phase oscillator with multiple oscillators that are magnetically coupled to each other for generating oscillation signals at different phases. The apparatus may also be, for example, a phase interpolator for combining input signals.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: February 14, 2017
    Assignee: Rambus Inc.
    Inventors: Mohammad Hekmat, Farshid Aryanfar, Kambiz Kaviani
  • Alternate access to DRAM data using cycle stealing
    Patent number: 9570146
    Abstract: A method for operating a DRAM is provided. The method includes initializing a dynamic random access memory (“DRAM”) array from a host controller, which is coupled to the DRAM array. The method includes isolating the dynamic random access memory array from a host controller and allowing a host computer to wait for a selected time period greater than the tRFC to define an alternate access time. The method includes initiating an access command to the DRAM array during the alternate access time.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: February 14, 2017
    Assignee: Rambus Inc.
    Inventor: Christopher Haywood
  • On-die termination of address and command signals
    Patent number: 9570129
    Abstract: A system has a plurality of memory devices arranged in a fly-by topology, each having on-die termination (ODT) circuitry for connecting to an address and control (RQ) bus. The ODT circuitry of each memory device includes a set of one or more control registers for controlling on-die termination of one or more signal lines of the RQ bus. A first memory device includes a first set of one or more control registers storing a first ODT value, for controlling termination of one or more signal lines of the RQ bus by the ODT circuitry of the first memory device, and a second memory device includes a second set of one or more control registers storing a second ODT value different from the first ODT value, for controlling termination of one or more signal lines of the RQ bus by the ODT circuitry of the second memory device.
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: February 14, 2017
    Assignee: Rambus Inc.
    Inventors: Ian Shaeffer, Kyung Suk Oh
  • Drift adjustment in timing signal forwarded from memory controller to memory device based on a detected phase delay occurring on a second timing signal with a different frequency
    Patent number: 9568942
    Abstract: A memory system in which a timing drift that would occur in distribution of a first timing signal for data transport in a memory device is determined by measuring the actual phase delays occurring in a second timing signal that has a frequency lower than that of the first timing signal and is distributed in one or more circuits mimicking the drift characteristics of at least a portion of distribution of the first timing signal. The actual phase delays are determined in the memory device and provided to a memory controller so that the phases of the timing signals used for data transport may be adjusted based on the determined timing drift.
    Type: Grant
    Filed: December 7, 2015
    Date of Patent: February 14, 2017
    Assignee: Rambus Inc.
    Inventors: Jun Kim, Pak Shing Chau, Wayne S. Richardson
  • Memory with deferred fractional row activation
    Patent number: 9570126
    Abstract: Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the subrow to be activated.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: February 14, 2017
    Assignee: Rambus Inc.
    Inventors: James E. Harris, Thomas Vogelsang, Frederick A. Ware, Ian P. Shaeffer
  • Testing through-silicon-vias
    Patent number: 9570196
    Abstract: Embodiments generally relate to integrated circuit devices having through silicon vias (TSVs). In one embodiment, an integrated circuit (IC) device includes a field of TSVs and an address decoder that selectably couples at least one of the TSVs to at least one of a test input and a test evaluation circuit. In another embodiment, a method includes selecting one or more TSVs from a field of TSVs in at least one IC device, and coupling each selected TS V to at least one of a test input and a test evaluation circuit.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: February 14, 2017
    Assignee: Rambus Inc.
    Inventors: Thomas Vogelsang, William N. Ng, Frederick A. Ware
  • In-band status encoding and decoding using error correction symbols
    Patent number: 9571231
    Abstract: A status encoder generates a checksum that encodes a status condition together with the checksum of an associated message. A receiver determines an inverse transformation that when applied to the received status-encoded checksum recovers the parity information associated with the codeword. The status condition can then be recovered based on the selection of the inverse transformation that correctly recovers the parity information from the status-encoded checksum. Beneficially, the status condition can be encoded without requiring additional signal lines or lengthening the codeword relative to conventional error correction devices.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: February 14, 2017
    Assignee: Rambus Inc.
    Inventors: John Eric Linstadt, Frederick A. Ware
  • Interface with variable data rate
    Patent number: 9569396
    Abstract: A device includes a transmitter coupled to a node, where the node is to couple to a wired link. The transmitter has a plurality of modes of operation including a calibration mode in which a range of communication data rates over the wired link is determined in accordance with a voltage margin corresponding to the wired link at a predetermined error rate. The range of communication data rates includes a maximum data rate, which can be a non-integer multiple of an initial data rate.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: February 14, 2017
    Assignee: Rambus Inc.
    Inventors: Yohan U. Frans, Hae-Chang Lee, Brian S. Leibowitz, Simon Li, Nhat M. Nguyen
  • Methods and apparatuses for addressing memory caches
    Patent number: 9569359
    Abstract: A cache memory includes cache lines to store information. The stored information is associated with physical addresses that include first, second, and third distinct portions. The cache lines are indexed by the second portions of respective physical addresses associated with the stored information. The cache memory also includes one or more tables, each of which includes respective table entries that are indexed by the first portions of the respective physical addresses. The respective table entries in each of the one or more tables are to store indications of the second portions of respective physical addresses associated with the stored information.
    Type: Grant
    Filed: February 22, 2012
    Date of Patent: February 14, 2017
    Assignee: Rambus Inc.
    Inventors: Trung Diep, Hongzhong Zheng
  • Resistance change memory cell circuits and methods
    Patent number: 9570171
    Abstract: The gate of the access transistor of a 1 transistor 1 resistor (1T1R) type RRAM cell is biased relative to the source of the access transistor using a current mirror. Under the influence of a voltage applied across the 1T1R cell (e.g., via the bit line), the RRAM memory element switches from a higher resistance to a lower resistance. As the RRAM memory element switches from the higher resistance to the lower resistance, the current through the RRAM cell switches from being substantially determined by the higher resistance of the RRAM device (while the access transistor is operating in the linear region) to being substantially determined by the saturation region operating point of the access transistor.
    Type: Grant
    Filed: September 26, 2015
    Date of Patent: February 14, 2017
    Assignee: Rambus Inc.
    Inventor: Brent Haukness