Abstract: In a contact structure to a source/drain region (28) nearby a gate electrode (22), a contact sidewall through a thick dielectric is laterally displaced away from the S/D region to widen the contact; the contact sidewall is located over the gate electrode A remnant (60a) of a doped silicon layer overlies the S/D and rises up along the sidewall of gate electrode insulation and onto insulation atop the gate electrode, and is insulated from the gate electrode thereby. The doped silicon acting as a dopant for the source/drain region. A nitride, preferably Si.sub.3 N.sub.4, is located under the thick dielectric and over part of the gate electrode insulation. The Si.sub.3 N.sub.4 adjoins the doped silicon to enclose the top and sides of the gate electrode with nitride. The bottom of the contact is formed by the doped silicon at some locations and by the nitride at other locations. The contact sidewall through the thick dielectric preferably overlies the Si.sub.3 N.sub.4 but not the doped silicon.

Abstract: A monolithic semiconductor integrated circuit-ferroelectric device is disclosed together with the method of manufacturing same. The ferroelectric device preferably consists of a layer of stable ferroelectric potassium nitrate disposed between electrical contacts positioned on opposite surfaces of the ferroelectric layer. The ferroelectric layer has a thickness of less than 110 microns, and preferably falling within a range of from 100 Angstrom units to 25,000 Angstrom units. The process of manufacturing the monolithic structure is multi-stepped and is particularly adapted for fabricating a potassium nitrate ferroelectric memory on a semiconductor integrated circuit.

Abstract: A ferroelectric capacitor for a memory device including a substrate, a bottom electrode and a top electrode. Between the bottom and top electrodes is either an alternating plurality of layers of ferroelectric material and intermediate electrodes or a plurality of layers of ferroelectric material. A method for forming the same through establishing one layer over the other is also disclosed.

Abstract: A reaction barrier is formed at an interface region between adjacent layers of a multilayer composite integrated circuit by implanting one or more active ionic species at energies effective to place the ionic species at or near the interface. A further step may include annealing the structure formed above to promote efficacy of the reaction barrier.

Abstract: In a multi-layered integrated memory circuit, a method for using sacrificial layers and insulating "sticks" is disclosed to provide a contact between two layers, where the contact does not short to an intervening layer. This invention provides this with minimal extra processing by using sacrificial layers with appropriate etch and etch stop properties. As these layers are etched, additional layers which alternate in the same conducting/insulating pattern are exposed. Each etch stops on either a conductive or insulative layer. A contact layer may then be deposited which connects the uppermost capacitor plate to the pass transistor of the memory cell.

Abstract: A ferroelectric capacitor for an integrated circuit includes a stack formed by a layer of a noble metal, a layer of a conducting oxide, a layer of a ferroelectric material, another layer of a conducting oxide and another layer of a noble metal. The capacitor can also have another layer of conducting oxide located over the top layer of noble metal and below the first layer of the noble metal. A method of forming the same through establishing one layer over the other and annealing each layer is also disclosed.

Abstract: A constant current power supply circuit for an integrated circuit memory which is well suited for driving a high capacitance load, such as a large number of sense amplifiers. A first circuit provides a constant current source and a second "current mirror" circuit provides an output current proportionate to the first circuit, but at a higher desired level of current. The constant current circuit is achieved using two cross-coupled FET transistors and two resistances such that the conductivity of each transistor is inversely related to the conductivity of the other. The circuit reaches a constant current equilibrium which is largely independent of operating voltage or load, but rather depends on the relative values of the components.

Abstract: A voltage reference generated for an integrated circuit which produces a source of reference voltage which is self-compensated for variations in operating voltage (V.sub.cc) or in transistor threshold voltages (V.sub.T). The circuit uses a voltage divider coupled between V.sub.cc and ground and has first and second FET transistors. A faced control circuit is coupled to control the conductivity of the first transistor, and the second control circuit is coupled to control the conductivity of the second transistor. The first control circuit produces a control voltage which varies as a function of variations in V.sub.cc, while the second control circuit also provides a control voltage wherein variations are a function of variations in V.sub.cc, but in an opposite direction. Hence, the second control voltage is configured so that variations in V.sub.cc cause the second transistor to compensate for changes in operation of the first transistor, so that the reference voltage remains substantially constant.

Abstract: An improved DRAM memory cell uses ferroelectric material as the dielectric between capacitor plates. Preferably polycrystalline PZT or a perovskite is used for the ferroelectric, and the polar axes of the dipoles in the ferroelectric material in relaxed position are not aligned with the direction of the resulting electric field when voltage is applied to the capacitor plates. Preferably, the dipole orientation is in the plane of the ferroelectric film so that when a write voltage is removed from the capacitor plate, the dipoles tend to relax to a non-aligned position. When the cell is read or refreshed, increased charge is drawn from the bit line and resides on the capacitor plate in order to reorient the relaxed dipoles. The charge developed on the plate hence is magnified.

Abstract: In a multi-layered integrated memory circuit, a method for using sacrificial layers and insulating "sticks" is disclosed to provide a contact between two layers, where the contact does not short to an intervening layer. This invention provides this with minimal extra processing by using sacrificial layers with appropriate etch and etch stop properties. As these layers are etched, additional layers which alternate in the same conducting/insulating pattern are exposed. Each etch stops on either a conductive or insulative layer. A contact layer may then be deposited which connects the uppermost capacitor plate to the pass transistor of the memory cell.

Abstract: A trench capacitor which has a plurality of capacitor plates separated by a dielectric within a trench on a substrate. A plate located closest to the wall of the trench may be a field shield and tied everywhere to ground. The other plate may be polysilicon. Said other plate may be tied to a source of variable potential. A plurality of sacrificial layers are established over the structure and the structure thus formed is then patterened and etched. A pass transistor is formed adjacent to the trench capacitor, and a connecting layer is established connecting the other plate of the trench capacitor to the source/drain region of the pass transistor. The connecting layer makes electrical contact to the other capacitor plate and source/drain of the pass transistor and is insulated from other layers in the capacitor and pass transistor. Bit lines and word lines can then be added, as known in the art.

Abstract: In a contact structure to a source/drain region (28) nearby a gate electrode (22), a contact sidewall through a thick dielectric is laterally displaced away from the S/D region to widen the contact; the contact sidewall is located over the gate electrode. Titanium silicide (34) is located upon the S/D. A remnant (36a) of a (conductive) TiN layer overlies the silicide and rises up along the sidewall of gate electrode insulation and onto insulation atop the gate electrode, and is insulated from the gate electrode thereby. A further nitride, preferably Si.sub.3 N.sub.4, is located under the thick dielectric and over part of the gate electrode insulation. The Si.sub.3 N.sub.4 adjoins the TiN to enclose the top and sides of the gate electrode with nitride. The bottom of the contact is formed by one nitride at some locations and by the other nitride at other locations. The contact sidewall through the thick dielectric preferably overlies the Si.sub.3 N.sub.4 but not the TiN.

Abstract: A monolithic semiconductor integrated circuit-ferroelectric device is disclosed together with the method of manufacturing same. The ferroelectric device preferably consists of a layer of stable ferroelectric potassium nitrate disposed between electrical contacts positioned on opposite surfaces of the ferroelectric layer. The ferroelectric layer has a thickness of less than 110 microns, and preferably falling within a range of from 100 Angstrom units to 25,000 Angstrom units. The process of manufacturing the monolithic structure is multi-stepped and is particularly adapted for fabricating a potassium nitrate ferroelectric memory on a semiconductor integrated circuit.

Abstract: Disclosed is a multilayer capacitor structure in an integrated circuit, including a first electrode constructed by forming at least one layer over a substrate and forming a plate layer over the previous layer(s). A dielectric layer is formed over this first electrode, and a second electrode is established over the dielectric layer by forming a plate layer over the dielectric layer, and forming at least one additional layer over the plate layer. Each layer may serve one or more functions. Also disclosed is a further embodiment including constructing a first electrode by forming at least one layer on a substrate, forming a plate layer over the previous layer(s), and forming a dielectric layer over the first electrode. The resulting structure is then heated, preferably in an oxygen ambient, to oxidize the lower layer. A second electrode can then be formed over the dielectric layer.

Abstract: A transpolarizer is employed as a programmable capacitance divider. Two ferroelectric capacitors are coupled in series to form a common node and two extreme poles. The polarization of the two capacitors is set by grounding the two poles and then bringing them both up to VCC while impressing a voltage at the common node corresponding to data to be stored. Therefore, while one pole is held at VSS, the other pole is pulsed from VSS to VCC with the common node floating. A voltage develops at the common node which is above or below the midpoint between VSS and VCC, and will be indicative of the stored data. The capacitance divider is programmed in accordance with data. One such divider is added to a DRAM memory cell to form a shadow DRAM cell. Two such dividers are added to a static RAM memory cell to form a shadow static RAM cell. The same divider arrangement is operable in both volatile and non-volatile modes. An improvement arises by using PZT as dielectric in 54:46 mole ratio.

Abstract: A transpolarizer is employed as a programmable capacitance divider. Two ferroelectric capacitors are coupled in series to form a common node and two extreme poles. The polarization of the two capacitors is set by grounding the two poles and then bringing them both up to VCC while impressing a voltage at the common node corresponding to data to be stored. Therefore, while one pole is held at VSS, the other pole is pulsed from VSS to VCC with the common node floating. A voltage develops at the common node which is above or below the midpoint between VSS and VCC, and will be indicative of the stored data. The capacitance divider is programmed in accordance with data. One such divider is added to a DRAM memory cell to form a shadow DRAM cell. Two such dividers are added to a static RAM memory cell to form a shadow static RAM cell. The same divider arrangement is operable in both volatile and non-volatile modes. An improvement arises by using PZT as dielectric in 54:46 mole ratio.

Abstract: A transpolarizer is employed as a programmable capacitance divider. Two ferroelectric capacitors are coupled in series to form a common node and two extreme poles. The polarization of the two capacitors is set by grounding the two poles and then bringing them both up to VCC while impressing a voltage at the common node corresponding to data to be stored. Therefore, while one pole is held at VSS, the other pole is pulsed from VSS to VCC with the common node floating. A voltage develops at the common node which is above or below the midpoint between VSS and VCC, and will be indicative of the stored data. The capacitance divider is programmed in accordance with data. One such divider is added to a DRAM memory cell to form a shadow DRAM cell. Two such dividers are added to a static RAM memory cell to form a shadow static RAM cell. The same divider arrangement is operable in both volatile and non-volatile modes. An improvement arises by using PZT as dielectric in 54:46 mole ratio.

Abstract: Polarization retention of a ferroelectric material in a memory cell is improved by open circuiting the write pulse. The depolarizing field is reduced by allowing charge to dissipate through the ferroelectric material, causing a polarizing field.

Abstract: A ferroelectric memory cell has one capacitor isolated from bit lines by two transistors, one on each side. The cell is read by pulsing the capacitor in one direction, then the other, storing developed charge on other capacitors or the like, and comparing voltages.

Abstract: A semiconductor memory uses cells with a ferroelectric capacitor having one plate coupled to a bit line by a FET and another plate coupled to a plate line. A pulse on the plate line causes the bit line to change voltage based on the state of the cell. A dummy cell arrangement is disclosed using one capacitor per cell, and another embodiment uses two capacitors per cell with no dummy. The cells cooperate with a sense amplifier and timing signals so that they are self restoring.