Abstract: A fast block write command includes providing an RFID tag having a memory, and using a stored address pointer to point to a known address in the memory, wherein the stored address pointer points to a starting address at a known safe block in the memory. The method is performed without an intermediate buffer. The received data is written to the known safe block and a cyclic redundancy check is computed on the received data. If the cyclic redundancy check matches, the received data is retained and the stored address pointer is updated. If the cyclic redundancy check does not match, the stored address pointer is kept for a future write operation. Further block writes can be disallowed after an initial successful block write.

Abstract: An array of ferroelectric memory cells that allows imprint mitigation includes ferroelectric memory cells respectively coupled to word lines, plate lines, and bit lines; a word line driver for driving the word lines; a plate line driver for driving the plate lines; a bit line driver for driving the bit lines; and an isolation device driver for driving isolation devices coupled between the bit lines and a plurality of bit lines. The method for mitigating imprint includes coupling the bit lines to a respective plurality of sense amplifiers, turning on a word line and pulsing a plate line associated with a row of ferroelectric memory cells, disconnecting the bit lines from the respective sense amplifiers, driving the plate line low and the bit lines high, driving the plate line high and the bit lines low, driving the plate line low and floating the bit lines, driving the bit lines with the sense amplifier, and turning off the word line and precharging the bit lines.

Abstract: A non-volatile memory cell and related system utilize ferroelectric capacitors as data storage elements. Circuitry is provided for writing to a single ferroelectric capacitor storage element, as well as to dual storage elements operating inversely. The storage elements are read by use of a sense amplifier in a configuration which automatically restores the original data states, thereby eliminating the need for a subsequent restore operation. Memory systems are described which include circuitry for driving bit lines, word lines and drive lines to accomplish both the write and read operations.

Abstract: An array of ferroelectric memory cells that allows imprint mitigation includes ferroelectric memory cells respectively coupled to word lines, plate lines, and bit lines; a word line driver for driving the word lines; a plate line driver for driving the plate lines; a bit line driver for driving the bit lines; and an isolation device driver for driving isolation devices coupled between the bit lines and a plurality of bit lines. The method for mitigating imprint includes coupling the bit lines to a respective plurality of sense amplifiers, turning on a word line and pulsing a plate line associated with a row of ferroelectric memory cells, disconnecting the bit lines from the respective sense amplifiers, driving the plate line low and the bit lines high, driving the plate line high and the bit lines low, driving the plate line low and floating the bit lines, driving the bit lines with the sense amplifier, and turning off the word line and precharging the bit lines.

Abstract: A non-volatile memory cell and related system utilize ferroelectric capacitors as data storage elements. Circuitry is provided for writing to a single ferroelectric capacitor storage element, as well as to dual storage elements operating inversely. The storage elements are read by use of a sense amplifier in a configuration which automatically restores the original data states, thereby eliminating the need for a subsequent restore operation. Memory systems are described which include circuitry for driving bit lines, word lines and drive lines to accomplish both the write and read operations.

Abstract: The signal margin of a small array 2T/2C memory is increased by writing the ferroelectric load capacitors on the bit lines to complementary states.

Abstract: A power-on reset circuit includes a first PNP transistor having an emitter, a base, and a collector coupled to ground; a second PNP transistor having an emitter coupled to the base of the first transistor, and a base and collector coupled to ground; a third PNP transistor having an emitter, a base coupled to the base of the first transistor, and a collector coupled to ground; a first resistor coupled between VDD and an internal node; a second resistor coupled between VDD and the emitter of the first transistor; a third resistor coupled between the internal node and the emitter of the third transistor; and a comparator having a first input coupled to the internal node and a second input coupled to the emitter of the first transistor for generating a power-on reset signal.

Abstract: A power-on reset circuit includes a first PNP transistor having an emitter, a base, and a collector coupled to ground; a second PNP transistor having an emitter coupled to the base of the first transistor, and a base and collector coupled to ground; a third PNP transistor having an emitter, a base coupled to the base of the first transistor, and a collector coupled to ground; a first resistor coupled between VDD and an internal node; a second resistor coupled between VDD and the emitter of the first transistor; a third resistor coupled between the internal node and the emitter of the third transistor; and a comparator having a first input coupled to the internal node and a second input coupled to the emitter of the first transistor for generating a power-on reset signal.

Abstract: The signal margin of a small array 2T/2C memory is increased by writing the ferroelectric load capacitors on the bit lines to complementary states.

Abstract: A ferroelectric reference circuit generates a reference voltage proportional to (P+U)/2 and is automatically centered between the bit line voltages corresponding to the P term and the U term across wide temperature and voltage ranges. To avoid fatiguing the reference ferroelectric capacitors generating (P+U)/2, the reference voltage is refreshed once every millisecond. To eliminate the variation of the reference voltage due to the leakage in the ferroelectric capacitors during this period of time, the reference voltage generated from the reference ferroelectric capacitors is digitized when it is refreshed. The digital value is fixed and converted to an analog value which is then fed into sense amplifiers for resolving the data states. The reference voltage is automatically at the center of the switching (P) and non-switching (U) signals and therefore the signal margin is maximized.

Abstract: An encoder utilizes a coding method for use with ferroelectric or other nonvolatile counters which are subject to imprint ensures that all of the bits in the code are frequently switched and not left in a fixed data state. The general coding equation for this method is such that: for an even integer n, it is represented by the conventional binary code of n/2; for an odd integer n, it is represented by the conventional binary code of the one's compliment of (n?1)/2. With this method, every bit switches to its compliment when counting from an even number to an odd number so that imprint is substantially reduced.

Abstract: An encoder utilizes a coding method for use with ferroelectric or other nonvolatile counters which are subject to imprint ensures that all of the bits in the code are frequently switched and not left in a fixed data state. The general coding equation for this method is such that: for an even integer n, it is represented by the conventional binary code of n/2; for an odd integer n, it is represented by the conventional binary code of the one's compliment of (n?1)/2. With this method, every bit switches to its compliment when counting from an even number to an odd number so that imprint is substantially reduced.

Abstract: An encoder utilizes a coding method for use with ferroelectric or other nonvolatile counters which are subject to imprint ensures that all of the bits in the code are frequently switched and not left in a fixed data state. The general coding equation for this method is such that: for an even integer n, it is represented by the conventional binary code of n/2; for an odd integer n, it is represented by the conventional binary code of the one's compliment of (n?1)/2. With this method, every bit switches to its compliment when counting from an even number to an odd number so that imprint is substantially reduced.

Abstract: A counting scheme for a non-volatile counter includes automatic point-of-reference generation implemented in a state machine. Two state variables are used to store the rotation history of the magnet. One variable stores the previous position of the magnet and the other stores the net angle traveled by the magnet from the reference point. The first pulse location after the counter is reset is automatically selected as the reference point until the next counter reset. When the nonvolatile counter counts up or down, i.e. when the magnet travels 360° in either direction, the second state variable is set to zero and the first state variable is set to the reference point, indicating the start of a new revolution.

Abstract: A non-volatile counter circuit includes a state machine having a first input for receiving one or more control signals, a second input for receiving a current count value, a third input for receiving historical information, and an output for providing a next count value and an up/down control signal, and a non-volatile counter having an input coupled to the output of the state machine, and an output for providing a non-volatile count value. The non-volatile counter can be implemented onto a single integrated circuit using ferroelectric memory technology. The non-volatile counter circuit includes a first power supply node and a second power supply node for receiving power for operating the non-volatile-counter circuit through a first power supply or a second power supply, or both. The first and second power supplies can be low energy power supplies such as that provided by a sensor, or can be conventional power supplies.

Abstract: A ferroelectric reference circuit generates a reference voltage proportional to (P+U)/2 and is automatically centered between the bit line voltages corresponding to the P term and the U term across wide temperature and voltage ranges. To avoid fatiguing the reference ferroelectric capacitors generating (P+U)/2, the reference voltage is refreshed once every millisecond. To eliminate the variation of the reference voltage due to the leakage in the ferroelectric capacitors during this period of time, the reference voltage generated from the reference ferroelectric capacitors is digitized when it is refreshed. The digital value is fixed and converted to an analog value which is then fed into sense amplifiers for resolving the data states. The reference voltage is automatically at the center of the switching (P) and non-switching (U) signals and therefore the signal margin is maximized.

Abstract: Various logic elements such as SR flip-flops, JK flip-flops, D-type flip-flops, master-slave flip-flops, parallel and serial shift registers, and the like are converted into non-volatile logic elements capable of retaining a current output logic state even though external power is removed or interrupted through the strategic addition of ferroelectric capacitors and supporting circuitry. In each case, the building blocks of a cross-coupled sense amplifier are identified within the logic element and the basic cell is modified and/or optimized for sensing performance.

Abstract: A column decoder cell layout for use in a 1T/1C ferroelectric memory array includes a first column decoder section having two input nodes for receiving a first input/output signal and a first inverted input/output signal, two output nodes for providing a fist bit line signal and a first inverted bit line signal, and a column decode node for receiving a column decode signal, a second column decoder section having two input nodes for receiving a second input/output signal and a second inverted input/output signal, two output nodes for providing a second bit line signal and a second inverted bit line signal, and a column decode node for receiving the column decode signal, wherein the width of the column decoder cell is substantially the same as the width of two columns of 1T/1C memory cells used in the array.

Abstract: A bottom electrode structure and manufacturing method is described for producing crystallographically textured iridium electrodes for making textured PZT capacitors that enables enhanced ferroelectric memory performance. The use of seed layers originating from hexagonal crystal structures with {0001} texture provides a smooth surface for growth of {111} textured iridium, which exhibits the face-centered cubic (“FCC”) structure. This seeding technique results in {111} textured iridium with a small surface roughness relative to the film thickness. The highly textured iridium supports {111} textured PZT dielectric layer growth. Textured PZT exhibits enhanced switched polarization, reduced operating voltage and also improves the reliability of PZT capacitors used in FRAM® memory and other microelectronic devices.

Abstract: A bottom electrode structure and manufacturing method is described for producing crystallographically textured iridium electrodes for making textured PZT capacitors that enables enhanced ferroelectric memory performance. The use of seed layers originating from hexagonal crystal structures with {0001} texture provides a smooth surface for growth of {111} textured iridium, which exhibits the face-centered cubic (“FCC”) structure. This seeding technique results in {111} textured iridium with a small surface roughness relative to the film thickness. The highly textured iridium supports {111} textured PZT dielectric layer growth. Textured PZT exhibits enhanced switched polarization, reduced operating voltage and also improves the reliability of PZT capacitors used in FRAM® memory and other microelectronic devices.