Abstract: A measurement method for capacitance includes the following steps. First, a voltage on at least one end of a to-be-measured capacitor is switched in response to a first set of clock signals such that a level of an integrated voltage is adjusted from a start voltage level to an end voltage level in a first integration period, wherein a capacitance of the to-be-measured capacitor is relevant to a difference between the end voltage level and the start voltage level. Next, the level of the integrated voltage is adjusted from the end voltage level to the start voltage level in a second integration period in response to a second set of clock signals. Then, the capacitance of the to-be-measured capacitor is obtained according to the first and second integration periods and a known characteristic parameter.

Abstract: The present invention provides a dual triggered silicon controlled rectifier (DTSCR) including: a semiconductor substrate, an N-well, a P-well, a first N+ diffusion region and a first P+ diffusion region, a second N+ diffusion region and a second P+ diffusion region; a third P+ diffusion region, positioned in one side of the DTSCR and across the N-well and the P-well; a third N+ diffusion region, positioned in another side of the DTSCR and across the N-well and the P-well; a first gate, positioned above the N-well between the second and the third P+ diffusion regions, utilized as a P-type trigger node to receive a first trigger current or a first trigger voltage; and a second gate, positioned above the P-well between the first and the third N+ diffusion regions, utilized as an N-type trigger node to receive a second trigger current or a second trigger voltage.

Abstract: The invention discloses a source driver. The source driver comprises a plurality of channels and a control module. Each of the plurality of channels comprises an output buffer, an output pad, a driving switch, and a charge sharing switch. The control module is used to control a gate signal of the driving switch or the charge sharing switch in each channel to be changed linearly. By doing so, a peak current generated by the source driver can be lowered to reduce the electromagnetic interference (EMI).

Abstract: An assembly structure is provided. The assembly structure includes a first substrate, a second substrate and a medium layer disposed between the first and second substrates. The medium layer includes a side edge, and the second substrate includes at least one lead wire. When the second substrate is disposed on the medium layer, the lead wire of the second substrate is relatively oblique to the side edge of the medium layer.

Abstract: A frame rate control (FRC) method is provided for driving a number of pixels according to a number of pixels data. The pixels include a number of first color sub-pixels. In this method, the dithering process is performed to the pixels data in two frames according to two basic matrixes respectively. In one of the two frames, the numbers of the first color sub-pixels, driven by the positive pixel voltages and the negative pixel voltages and to which the dithering process has been performed, are the same in substantiality. Further, in the other of the two frames, the numbers of the first color sub-pixels, driven by the positive pixel voltages and the negative pixel voltages and to which the dithering process has been performed, are also the same in substantiality.

Abstract: An optical tweezers lifting apparatus is provided. The optical tweezers lifting apparatus includes an optical tweezers and a particle-lifting device. The particle-lifting device includes a substrate and a plurality of electrodes that are disposed on the bottom of a flow path in the substrate. When a dielectrophoresis (DEP) solution with a plurality of floating particles is conducted into the flow path and upon those electrodes and a voltage is applied to these electrodes, these particles would be driven by a negative DEP force to move upward to a specific depth in the flow path. Meanwhile, the optical tweezers of the apparatus is selectively focused at the specific depth in the flow path.

Abstract: A level shifter circuit includes a level shifter, an inverter, a first switch circuit and a second switch circuit. The level shifter includes a first transistor, a second transistor, a third transistor and a fourth transistor. The inverter receives an input signal and thus generates an inversion input signal. The first transistor and the second transistor are respectively controlled by the input signal and an output signal to output an inversion output signal. The third transistor and the fourth transistor are respectively controlled by the inversion input signal and the inversion output signal to output an output signal. The first switch circuit is coupled to the level shifter and turns off the fourth transistor when the third transistor is turned on. The second switch circuit is coupled to the level shifter, and turns off the second transistor when the first transistor is turned on.

Abstract: A capacitance measurement circuit and a capacitance measurement method thereof. The capacitance measurement circuit for measuring a capacitor under test includes a capacitance to time unit, a continuous time integrator and an analog to digital converter. The capacitance to time unit generates a first clock signal and a second clock signal reverse to the first clock signal according to a first charge time of the capacitor under test and a second charge time of a variable capacitor. The continuous time integrator receives the first clock signal and outputs an integral signal according to the first clock signal. When the number of clocks of the second clock signal is equal to a default value, the analog to digital converter outputs a digital signal corresponding to a capacitance difference between the capacitor under test and the variable capacitor according to the integral signal.

Abstract: The invention discloses a driving circuit system and a method of elevating a slew rate of an operational amplifier. The driving circuit system comprises an operational amplifier, a judging module and a bias enhancing module. The operational amplifier has an input stage driven by a bias current. The bias enhancing module is electrically connected to the judging module and the input stage of the operational amplifier respectively. The judging module is used to generate a bias enhancing signal according to an edge-trigger of a control signal. When the bias enhancing module receives the bias enhancing signal, the bias enhancing module provides an additional current, which cooperates with the bias current, for driving the input stage of the operational amplifier, so as to elevating a slew rate of the operational amplifier.

Abstract: A capacitance evaluation circuit includes a capacitive voltage divider, an analog-to-digital converter (ADC) and a processing module. The capacitive voltage divider includes a switch circuit, a known capacitor and a capacitor under test. The switch circuit is controlled by first and second clock signals. A voltage variation at a first terminal of the known capacitor is coupled to a first terminal of the capacitor under test based on a conduction state of the switch circuit. The ADC converts a voltage on the first terminal of the capacitor under test into a digital signal. The processing module detects a capacitance and a capacitance variation of the capacitor under test according to the digital signal from the ADC and a parameter of the ADC.

Abstract: A flip-flop is provided. The flip-flop is used in a shift register in a source driver. The flip-flop is used to receive a first clock signal, an input signal and output an output signal. The output signal is fed back to the flip-flop. The flip-flop includes a flop core for receiving the input signal and output the output signal. When the input signal and the output signal are all disabled, the flop core is disabled to function. When the input signal or the output signal is enabled, the flop core is enabled to function to output the output signal.

Abstract: A source driving apparatus and a driving method thereof are provided. The source driving apparatus comprises an encoder and a source driver. The encoder encodes a video data with n bits to the encoded data according to encoding rules, such that the bit change in two adjacent grays is less than n. The source driver outputs a pixel voltage corresponding to the video data according to the encoded data.

Abstract: A receiving circuit is provided for receiving a data signal and a clock signal, which are RSDS signals, and outputting an output data signal to a data driver. The receiving circuit includes a data comparator, a data intermediate circuit, a clock comparator, a clock intermediate, and a flip-flop. The data comparator, driven with a data bias current, receives the data signal, and outputs a compared data signal. The clock comparator, driven with a clock bias current, receives the clock signal, and outputs a compared clock signal. The flip-flop receives the compared data signal via the data intermediate circuit and the compared clock signal via the clock intermediate circuit. The phase difference between the compared data signal and the compared clock signal is improved by adjusting the data and the clock bias currents.

Abstract: A memory includes at least one memory cell. The memory cell includes a first set of bits and a second set of bits for respectively storing first sub-pixel data and second sub-pixel data of pixel data. The first set of bits has a first fail bit. A least significant bit of the first sub-pixel data is stored at the first fail bit.

Abstract: In an evaluation method, voltages at ends of a to-be-measured capacitor and a capacitance-adjustable circuit are switched in response to a first set of clock signals so as to adjust an integrated voltage to be a sum of the integrated voltage and a first difference voltage. Next, whether a first control event is received is judged. If not, the previous step is performed. If yes, an integration operation is performed to switch a voltage of an end of a known capacitor in order to adjust the integrated voltage to be a sum of the integrated voltage and a second difference voltage. Next, whether an integrating period ends is judged. If not, the first step is repeated. If yes, a capacitance of the to-be-measured capacitor is obtained according to the number of times that the integration operation is performed in the integrating period and a capacitance of the known capacitor.

Abstract: A spread spectrum clock signal generator for spreading an input clock signal into an output clock signal includes a clock signal delay chain for delaying the input clock signal into a delay clock signal group having a plurality of delay clock signals, a modulation controller for outputting a counter clock signal control signal, a clock signal selection circuit for selecting, from the delay clock signal group, a modulation clock signal group having a plurality of modulation clock signals, a programmable counter for generating a counting value according to a counter clock signal, and a clock signal output unit for combining the modulation clock signals into the output clock signal according to the counting value, and further generating the counter clock signal, outputted to the programmable counter, according to the counter clock signal control signal.

Abstract: The invention discloses a controlling apparatus for a signal outputting circuit in an electronic system. The controlling apparatus includes a detecting circuit, a switch, and a controlling circuit. The detecting circuit is used for detecting whether the electronic system has an abnormal condition. The switch is electrically connected between a signal receiving terminal and the signal outputting circuit. The controlling circuit is electrically connected between the detecting circuit and the switch. Once the detecting circuit detects that the electronic system has the abnormal condition, the controlling circuit sets the switch into a high-impedance state.

Abstract: A current source includes a node, a biasing circuit, a loading circuit and a current mirror. The node has a specified voltage. The biasing circuit biases the specified voltage to be a first reference voltage. The loading circuit provides an equivalent resistor across the node and a second reference voltage to generate a reference current. The loading circuit includes a resistor and a metal oxide semiconductor field effect transistor (MOSFET). The resistor has a first temperature coefficient. The transistor operating in a linear region is controlled by a control voltage to turn on and to form a transistor resistor coupled with the resistor in series. The transistor resistor has a second temperature coefficient, wherein a temperature coefficient of the equivalent resistor is relevant to the first and second temperature coefficients. The current mirror receives the reference current and provides a mirrored current of the reference current as the output current.

Abstract: A light module is provided. The light module applied to a dark field microscope is used for illuminating an object. The light module includes a light beam, a reflection component and a condensing component. The light beam has several lights. The reflection component is used for converting the lights radiating along a beginning direction to a circular beam substantially radiating along the beginning direction. The circular beam passes through the condensing component and is focused on the object. A part of the circular beam passing through the condensing component is scattered by the object.

Abstract: A continuous testing device for testing the concentration of a target object in a fluid is provided. The continuous testing device includes a first chip, a signal source and a second chip. The first chip includes a separating unit and a reacting unit. The separating unit separates the target object from a non-target object in the fluid. The reacting unit enables the fluid having separated out the non-target object to react with a reagent. The signal source provides a signal passing through the fluid having reacted with the reagent. The second chip disposed at one side of the first chip includes a signal transducing element and a processing unit. The signal transducing element receives the signal passing through the fluid and outputs an electronic signal corresponding to the input signal. The processing unit acquires the concentration of the target object according to the electronic signal.