Abstract: A level shifter consisting of first to fifth transistors is provided. First ends of the first and second transistors are coupled to a first supply voltage. Control ends of third and fourth transistors respectively receive first and second input signals. First ends of the third and fourth transistors are respectively coupled to control ends of the second and first transistors, and are respectively coupled to second ends of the first and second transistors. Second ends of the third and fourth transistors are coupled to a second supply voltage. The first ends of the third and fourth transistors respectively output first and second output signals. A first end and a control end of the fifth transistor are coupled to the control ends of one and the other of the first and second transistors. A second end of the fifth transistor is coupled to the second supply voltage.

Abstract: A measurement method for capacitance includes the following steps. First, a voltage on at least one end of a to-be-measured capacitor is switched in response to a first set of clock signals such that a level of an integrated voltage is adjusted from a start voltage level to an end voltage level in a first integration period, wherein a capacitance of the to-be-measured capacitor is relevant to a difference between the end voltage level and the start voltage level. Next, the level of the integrated voltage is adjusted from the end voltage level to the start voltage level in a second integration period in response to a second set of clock signals. Then, the capacitance of the to-be-measured capacitor is obtained according to the first and second integration periods and a known characteristic parameter.

Abstract: An assembly structure is provided. The assembly structure includes a first substrate, a second substrate and a medium layer disposed between the first and second substrates. The medium layer includes a side edge, and the second substrate includes at least one lead wire. When the second substrate is disposed on the medium layer, the lead wire of the second substrate is relatively oblique to the side edge of the medium layer.

Abstract: A voltage-clamping device used in an operational amplifier is provided. The operational amplifier comprises a first transistor. The cross-voltage between the gate and the source of the first transistor is near to a specific voltage and the cross-voltage between the drain and the source of the first transistor is not equal to zero, so as to generate a big substrate current. The voltage-clamping device comprises a second transistor whose source and gate are respectively coupled to the drain of the first transistor and used for receiving a bias signal, so that the second transistor is biased in saturation region, and the voltage at the source of the second transistor is made equal to the difference between the bias signal and the threshold voltage of the second transistor. Thus, the cross-voltage between the drain and the source of the first transistor is reduced and the substrate current is reduced accordingly.

Abstract: A power management circuit includes a regulator circuit, a first frequency compensation circuit, a first switch circuit and a detection circuit. The regulator circuit includes a signal output end. The first switch circuit is turned on in response to an enabled first control signal such that the first frequency compensation circuit is coupled to the regulator circuit. The detection circuit determines whether an output capacitor is coupled to the signal output end, and generates the enabled first control signal to turn on the first switch circuit and connect the first frequency compensation circuit to the regulator circuit when the output capacitor is not coupled to the signal output end. Therefore, the regulator circuit is frequency compensated by the first frequency compensation circuit.

Abstract: The invention discloses an integrated circuit package. The integrated circuit package comprises a substrate having a first surface and a second surface opposite thereto and a first hole passing through the substrate from the first surface to the second surface. A plurality of conductive lines is disposed on a portion of the second surface of the substrate. A semiconductor chip is disposed above the second surface of the substrate, wherein a chamber is formed between the semiconductor chip and the substrate. A plurality of bonding pads are disposed on a side of the semiconductor chip which is toward the second surface of the substrate, wherein at least one of the bonding pads are electrically connected to one of the plurality of conductive lines. A first heat dissipation layer is disposed in the first hole, and extends into the chamber. A method for fabricating the integrated circuit package is also provided.

Abstract: The invention provides a semiconductor device package. The package includes a chip disposed on a supported board and a conductive path formed between the chip and the supported board, on the backside of the supported board, or on the chip, so that the conductive path does not have to go around a region where the chip is located. Accordingly, the dimensions of the semiconductor device package are reduced.

Abstract: The invention provides a fluid measuring apparatus, which includes a collector, a sensing circuit, and an electrochromic device electrically connected to the sensing circuit. When the concentration of a fluid flowing through the collector and between the sensing circuit varies, the color of the electrochromic device changes accordingly. Further, the electrochromic device includes an electrochromic material, and the sensing circuit includes a first electrode and a second electrode, wherein the first and the second electrodes are disposed in the collector and the electrochromic material is disposed on the first electrode. When the concentration of an electrolytic solution flowing between the first electrode and the second electrode varies, the color of the electrochromic material changes accordingly.

Abstract: An apparatus and a method for changing optical tweezers are provided. The apparatus includes a diffractive optical element (DOE), a mask unit and an objective lens. The DOE includes a plurality of phase delay patterns. The mask unit includes a plurality of mask patterns that correspond to the phase delay patterns, respectively, wherein at least a portion of the mask patterns are complementary. A laser beam passing through each phase diffractive pattern correspondingly passes through each mask pattern to generate a compound diffractive pattern. The objective lens receives the compound diffractive pattern and focuses it on an examining object to form an optical tweezers.

Abstract: An optical tweezers controlling device including a light source, an objective lens and a focus adjusting unit is provided. The focus adjusting unit disposed between the light source and the objective lens includes a mirror set and a zoom lens set. The mirror set has at least a mirror. The mirror is rotatable such that after a light of the light source is projected to the mirror, the reflective direction of the light reflected from the mirror is changeable. The zoom lens set has at least a zoom lens disposed in accordance with the mirror. By rotating the mirror or changing the focal length of the zoom lens, the focusing location of the light changes on the focal plane of the objective lens or in the front or the rear of the focal plane.

Abstract: An apparatus of generating an optical tweezers with momentum and method thereof and an optical tweezers photo-image for guiding particles are provided. The apparatus generates at least one optical tweezers on an examined object that carries at least one particle. The apparatus includes a laser source, a diffractive optical element and a convergent lens. The laser beam from the laser source passes through the diffractive optical element to produce a diffractive pattern. The laser beam is then received by the convergent lens and then to be focused on a plane of the examined object. The optic axis of the convergent lens is substantially not perpendicular to the plane of the examined object, so that the laser beam is projected onto the plane of the examined object in a skewed manner for providing a lateral momentum to move the particle.

Abstract: A scan driver for a liquid crystal display (LCD) includes first and second address logic units, first and second level shifters and a decoder. The first address logic unit enables an ith first address signal among N first address signals during a Kth clock period according to a control signal, wherein the number i is equal to a remainder of K/N. The second address logic unit enables a jth second address signal among M second address signals during the Kth clock period according to the control signal, wherein the number j is equal to a quotient of K/N plus 1. The first and second level shifters respectively increase swings of the first and second address signals. When the ith first address signal and the jth second address signal are enabled, the decoder enables a (j?1)×N+i)th scan signal among M×N scan signals.

Abstract: A shift register is provided for use in a data driver. The shift register includes a shift registering unit. The shift registering unit selectively receives a clock signal. The shift registering unit includes a flip-flop; and a first selection circuit. The first selection circuit selectively sends the clock signal to the flip-flop according to a first selection signal, wherein before the flip-flop receives a data signal that is enabled, the first selection circuit sends the clock signal to the flip-flop according to the first selection signal so that the flip-flop correctly outputs the enabled data signal according to the clock signal.

Abstract: A receiving circuit is provided for receiving a data signal and a clock signal, which are RSDS signals, and outputting an output data signal to a data driver. The receiving circuit includes a data comparator, a data intermediate circuit, a clock comparator, a clock intermediate, and a flip-flop. The data comparator, driven with a data bias current, receives the data signal, and outputs a compared data signal. The clock comparator, driven with a clock bias current, receives the clock signal, and outputs a compared clock signal. The flip-flop receives the compared data signal via the data intermediate circuit and the compared clock signal via the clock intermediate circuit. The phase difference between the compared data signal and the compared clock signal is improved by adjusting the data and the clock bias currents.

Abstract: A display array driving circuit is provided. The circuit includes a first memory block, a second memory block, and a main circuit. The first memory block stores the most significant bit (MSB) of the data of one pixel. The second memory block is utilized to store non-MSB bits of the data of the pixel. The main circuit retrieves the MSB of the data of the pixel from the first memory block when the display array is in a predetermined mode, for displaying the pixel data on the display array. In the predetermined mode, the main circuit does not retrieve the non-MSB bits of the data of the pixel, and power consumption is subsequently reduced.

Abstract: A voltage-clamping device used in an operational amplifier is provided. The operational amplifier comprises a first transistor. The cross-voltage between the gate and the source of the first transistor is near to a specific voltage and the cross-voltage between the drain and the source of the first transistor is not equal to zero, so as to generate a big substrate current. The voltage-clamping device comprises a second transistor whose source and gate are respectively coupled to the drain of the first transistor and used for receiving a bias signal, so that the second transistor is biased in saturation region, and the voltage at the source of the second transistor is made equal to the difference between the bias signal and the threshold voltage of the second transistor. Thus, the cross-voltage between the drain and the source of the first transistor is reduced and the substrate current is reduced accordingly.

Abstract: A digital-to-analog (D/A) converter comprises a decoder apparatus and an operational amplifier. The decoder apparatus comprises first and second decoder unit. The first decoder unit selects a voltage of first voltage set as first and second voltage in response to a value of first gray level set. The second decoder unit selects first border voltage of second voltage set as the first and the second voltages and second border voltage of that as the first and the second voltages in response to the maximum and the minimum value of second gray level set respectively. The second decoder unit further selects the first and the second boarder voltage as the first and the second voltage respectively in response to an intermediate value of the second gray level set. The operational amplifier generates a pixel voltage having level between the first and the second voltage accordingly.

Abstract: A flip-flop is provided. The flip-flop is used in a shift register in a source driver. The flip-flop is used to receive a first clock signal, an input signal and output an output signal. The output signal is fed back to the flip-flop. The flip-flop includes a flop core for receiving the input signal and output the output signal. When the input signal and the output signal are all disabled, the flop core is disabled to function. When the input signal or the output signal is enabled, the flop core is enabled to function to output the output signal.

Abstract: A power-on screen pattern correcting apparatus is for correcting start output data of output terminals of a source driver such that a power-on screen pattern of a display is substantially uniform. The correcting apparatus comprises a flip-flop, a first logic unit and a second logic unit. The flip-flop controls a level of an inner signal to be substantially equal to a low signal level in response to a low level of a power start signal. The first logic unit enables a first signal in response to the low level of the inner signal or a low level of a high-impedance control signal. The second logic unit enables a second signal such that the output terminals are coupled to a charge sharing line and the power-on screen pattern is uniform in response to the low level of the inner signal or a low level of a charge-sharing control signal.

Abstract: A method for generating chopper-stabilized signals includes the following steps. First, a voltage polarity control signal is received. Next, the voltage polarity control signal is sampled to obtain a sampling signal, and a voltage transformation manner of the voltage polarity inversion of the voltage polarity control signal is judged according to the sampling signal. Then, a frame transformation signal template is obtained according to the voltage transformation manner of the voltage polarity inversion of the voltage polarity control signal and the sampling signal. Next, the frame transformation signal template is compared with the sampling signal and a frame transformation signal is generated. Then, a first chopper-stabilized signal is outputted according to the frame transformation signal and the voltage polarity control signal.