Abstract: An electronic device includes a memory, a processor, and functional hardware. The memory includes a queue. The processor is configured to write a processing instruction into a target area of the queue. The functional hardware is configured to read the processing instruction from the target area and reserve the target area. The functional hardware generates a completion message according to the processing instruction, and writes the completion message into the target area after the processing instruction is executed. The completion message corresponds to the processing instruction.

Abstract: Disclosed is a method for maintaining operation log information stored in a non-volatile memory of a storage device. The method includes the steps of: configuring a buffer area of a volatile memory; caching the operation log information into the buffer area; writing the operation log information stored in the buffer area into a predetermined storage area of the non-volatile memory; repeatedly updating the operation log information to the predetermined storage area; and initializing the storage device, which includes the following steps of enabling a watchdog timer in a controller; fetching the latest operation log information by reading the predetermined storage area when the watchdog timer counts a predetermined time and the storage device does not complete the initialization; configuring the storage device to perform a force low-level formatting after the latest operation log information is fetched; and disabling the watchdog timer when the storage device completes the initialization.

Abstract: Disclosed are a storage device and a method for sudden power off recovery thereof. The method includes: performing a first snapshot operation on the storage device to obtain system information, and storing the system information and a first tag into a non-volatile memory when the storage device in an idle state; performing a second snapshot operation on the storage device to obtain system information of the storage device, and storing the system information and a second tag into the non-volatile memory when at least one of the following conditions occurring: updating a logical-to-physical mapping table in the non-volatile memory, executing a garbage collection operation, and programming a new block; searching the latest system information in the non-volatile memory when recovering supply of power; when determining that the searched system information includes the first tag, performing a lightweight sudden power off recovery operation in the storage device.

Abstract: A processing and storage circuit includes an internal bus, one or more first-level internal memory units, a central processing unit (CPU), one or more hardware acceleration engines, and an arbiter. The first-level internal memory unit is coupled to the internal bus. The CPU includes a second-level internal memory unit, and is configured to access the first-level internal memory unit via the internal bus, and when the CPU accesses data, the first-level internal memory unit is accessed preferentially. The hardware acceleration engine is configured to access the first-level internal memory unit via the internal bus. The arbiter is coupled to the internal bus, configured to decide whether the CPU or the hardware acceleration engine be allowed to access the first-level internal memory unit. The arbiter sets the priority of the CPU accessing the first-level internal memory unit to be over the hardware acceleration engine.

Abstract: A method for generating a random number, applied in a random number generator coupled to a flash memory is disclosed. the method comprises: selecting a plurality of cells from the flash memory; initializing the selecting cells of the flash memory; programming the selecting cells to obtain a plurality of first potential values of the selecting cells; re-initializing the selecting cells of the flash memory; re-programming the selecting cells to obtain a plurality of second potential values of the selecting cells; and processing the first potential values and the second potential values according to a predetermined algorithm to generating the random number.

Abstract: The present disclosure provides a redundancy method for a flash memory device. The flash memory device comprises multiple storage areas in which at least one storage area is configured as a temporary storage area for redundant operations. The method comprises: performing redundant operations to a first set of pages stored in one of the plurality of storage areas in a cache to generate an intermediate result; storing the intermediate result to the storage area of the at least one temporary storage area for redundant operation from the cache; performing redundant operations to the (m+1)th set of pages stored in one storage area the redundant operation result of and the first set of pages stored in the at least one temporary storage area for redundant operation to produce a final result in the cache; storing the final result to the corresponding pages in the (m+1)th set of pages from the cache.

Abstract: A method for adaptively identifying flash memory type includes driving a flash memory interface according to a predetermined configuration and a predetermined protocol of the flash memory interface to send a reading command to a flash memory module to obtain a flash memory identity by successfully reading the flash memory module; changing at least one of the configuration and the interface protocol of the flash memory interface then performing the obtaining the flash memory identity again until all preset adjustments have been tried; and storing the obtained flash memory identity and a firmware corresponding to the obtained flash memory identity to a designated address of a non-volatile memory when the flash memory module is successful read. The above automated method can solve the disadvantages of high cost and low manufacturing flexibility caused by conventional manual identification and re-burning of eFuses.

Abstract: The present invention provides a memory controller including an artificial intelligence (AI) module and a microprocessor. In the operations of the memory controller, the AI module receives a read command from a host device, and generates an auxiliary command according to the read command. The microprocessor is configured to select a first L2P mapping table according to a logical address included in the read command, and refer to the first L2P mapping table to read data from a memory module. The microprocessor is further configured to read a second L2P mapping table from the memory module according to the auxiliary command, wherein the second L2P mapping table does not include the logical address included in the read command.

Abstract: An electronic device includes: a storage device containing a target block having multiple word lines and multiple bit lines; a transmission interface configured to operably receive data to be written into the storage device; and a controller circuit including: an access circuit; and a flash memory control circuit configured to operably control the access circuit to write a first data into one or more pages connected with a first word line in the target block using a first program scheme, and to operably control the access circuit to write a second data into one or more pages connected with a second word line in the target block using a second program scheme, so that the first data and the second data are stored in the target block at the same time.

Abstract: A memory controller includes: an interface configured to operably communicate with a host device; a temperature detecting circuit configured to operably detect an ambient temperature, wherein when the ambient temperature is beyond a predetermined temperature range, the temperature detecting circuit generates a control signal; and a processing circuit coupled to the interface and the temperature detecting circuit, for selecting one of a plurality of data program schemes to program data into a first storage block of a flash memory according to the control signal.

Abstract: The present invention discloses a solid state drive (SSD) control device including: a multi-interface compatible physical layer circuit operable to generate a physical layer output signal according to a serializer/deserializer (SerDes) reception signal; and a processing circuit operable to make the solid state drive control device adapt to one of several interface types in accordance with the physical layer output signal.

Abstract: A memory device includes a memory module and a control module. The control module is coupled to the memory module and is configured to store data into the memory module according to a first mapping table. The control module includes a storing unit and a guaranteeing unit. The storing unit is configured to store the first mapping table. The guaranteeing unit is coupled to the storing unit and is configured to determine whether the first mapping table is correct or not. The guaranteeing unit is further configured to issue an error signal in a state where the first mapping table is incorrect.

Abstract: A memory controller includes an interface circuit and a control circuit. The interface circuit is configured to communicate with a host device. When the control circuit finishes executing N commands from the host device, the memory controller notifies the host device to release corresponding memory in the host device corresponding to the N commands, and N is a positive integer. The control circuit compares a data transmission speed of the interface circuit with a predetermined value to generate a comparison result, and the control circuit adjusts a value of N based on the comparison result.

Abstract: A data backup method for backing up target data, through a driver module, from a first storage device to a second storage device is disclosed. The first storage device includes a first storage unit that stores the target data, and a first control unit that accesses the first storage unit based on a first logical-to-physical mapping table. The second storage device includes a second storage unit and a second control unit that accesses the second storage unit based on a second logical-to-physical mapping table. The method includes steps of: reading the target data from the first storage unit without accessing the first logical-to-physical mapping table and transmitting the target data to the driver module; transmitting the target data to the second control unit; and writing the target data to the second storage unit without accessing the second logical-to-physical mapping table.

Abstract: The present invention discloses a solid state drive (SSD) control device including: a multi-interface compatible physical layer circuit operable to generate a physical layer output signal according to a serializer/deserializer (SerDes) reception signal; an input/output (I/O) circuit operable to generate at least one terminal output signal according to signal variation of at least one terminal; and a processing circuit operable to make the solid state drive control device adapt to one of several interface types in accordance with the physical layer output signal and/or the at least one terminal output signal.

Abstract: A data storage device includes a power line communication (PLC) circuit and a storage controller. The PLC circuit is coupled to a power line. The storage controller is coupled to the PLC circuit. The storage controller is configured to access a plurality of memory block. The PLC circuit is configured to carry at least one signal outputted from the storage controller on the power line, in order to transmit the at least one signal to an external device such that an operational state of the data storage device can be debugged/monitored.

Abstract: An apparatus and a method for accessing a plurality of memory blocks is disclosed. The An apparatus comprises: a memory circuit configured to store a recording table, wherein the recording table corresponds to quality index of the plurality of memory blocks; and a control circuit configured to group the plurality of memory blocks to a first memory group and a second memory group according to the quality index; to enable to access the memory blocks in the first memory group, and to disable to access the memory blocks in the second memory group.

Abstract: A memory controller includes: an interface configured to operably communicate with a host device; a temperature detecting circuit configured to operably detect an ambient temperature, wherein when the ambient temperature is beyond a predetermined temperature range, the temperature detecting circuit generates a control signal; and a processing circuit coupled to the interface and the temperature detecting circuit, for selecting one of a plurality of data program schemes to program data into a first storage block of a flash memory according to the control signal.

Abstract: An electronic device includes: a storage device containing a target block having multiple word lines and multiple bit lines; a transmission interface configured to operably receive data to be written into the storage device; and a controller circuit including: an access circuit; and a flash memory control circuit configured to operably control the access circuit to write a first data into one or more pages connected with a first word line in the target block using a first program scheme, and to operably control the access circuit to write a second data into one or more pages connected with a second word line in the target block using a second program scheme, so that the first data and the second data are stored in the target block at the same time.

Abstract: The present invention discloses a memory control device and method compatible to multiple types of interface the memory control device comprises: a multi-interface physical layer circuit configured to couple to a host, to receive a differential signal from the host, to detect at least one of characteristics of the differential signal to generate a physical layer output signal and to generate a physical layer output signal according to a detected result, wherein a frequency of the differential signal is higher than hundreds of KHz; and a processing circuit, coupled between the multi-interface physical layer circuit and a memory module, configured to receive the physical layer output signal from the multi-interface physical layer circuit, to determine the differential signal complies with one of a specification of an first type of interface and that of a second type of interface according to the physical layer output signal, and to adapt an operation mode of the memory control device to one of the multiple type