Abstract: A CORDIC processor has a plurality of stages, each of the stages having a X input, Y input, a sign input, a sign output, an X output, a Y output, a mode control input having a ROTATE or VECTOR value, and a stage number k input, each CORDIC stage having a first shift generating an output by shifting the Y input k times, a second shift generating an output by shifting X input k times, a multiplexer having an output coupled to the sign input when the mode control input is ROTATE and to the sign of the Y input when the mode input is VECTOR, a first multiplier forming the product of the first shift output and the multiplexer output, a second multiplier forming the product of the second shift output and an inverted the multiplexer output, a first adder forming the X output from the sum of the first multiplier output and the X input, and a second adder forming the Y output from the sum of the second multiplier output and the Y input.

Abstract: A channel smoothing filter with a finite impulse response (FIR) has a controller which reads parallel sample data out of an FFT memory in such a manner as to generate an even function, the sample data applied to a preamble equalizer accompanied by a preamble sign and zero, the preamble outputs coupled to three filter processors, each filter processor having four filter engines whose outputs are summed, the channel smoothing filter generating an a register output, the register input coupled to a summer which has as inputs: the first filter processor shifted by four, the second filter processor shifted by two, the third filter processor, and the register output. Coefficients for an edge filter and a central filter are provided in Zero Sign Shift (ZSS) format, and by selection of coefficients using a canonical signed digit (CSD) algorithm, no multipliers are required for the channel smoothing FIR filter.

Abstract: A clock selector operative on two clocks operating on different domains and responsive to a SELECT input provides a transition from a first clock to a second clock, and from a second clock to a first clock with a dead zone therebetween. The delay is provided by a doublet register having a first register coupled to a second register, the two registers operative on one of the clock domains. Additionally, a clock selector is operative on two clocks which are each accompanied by a clock availability signal where the state machine provides a variety of states to create a dead zone between selections, and to bring the state machine to a known state until a clock signal is again available.

Abstract: A transmit filter for a stream of OFDM symbols has a remapper, Infinite Impulse Response (IIR) filter and a controller, the transmit filter operating on a stream of OFDM symbols. The transmit filter accepts symbols to be transmitted, the re-mapper re-orders them, the IIR filters the re-ordered stream, and a controller provides an output by rearranging the filtered symbols. The incoming symbol stream contains a series of symbols, each followed by a guard interval, where each guard interval has a first Tg symbol interval, and a second Tg symbol interval, the remapper generating a re-ordered stream having a first Tg symbol interval, a second Tg symbol interval and the symbol, the output of the IIR filter thereby generating a filtered first Tg symbol, a filtered second Tg symbol, and a filtered symbol, and the controller forms the transmit output by discarding the filtered first Tg symbol and outputting, in sequence, the filtered second Tg symbol, the filtered symbol, and a copy of the filtered second Tg symbol.

Abstract: A filter for receiver and operative on a stream of OFDM symbols has a symbol timing identifier which indicates the time interval for each symbol and also indicates a non-truncation interval and a truncation interval of the stream of symbols. The stream of OFDM symbols is applied to an infinite impulse response (IIR) filter with a reset input for resetting internal registers such that during the non-truncation interval, the reset input is not asserted, and during the truncation interval of the stream of OFDM symbols, the reset input is asserted during the intervals between symbols, as identified by the symbol timing identifier.

Abstract: A reduced complexity maximum likelihood decoder receives a stream of received symbols Y accompanied by a channel estimate matrix H. A variable transformation part includes a first part which converts Y and H into Z and R by computing a matrix R having at least one non-zero element in a row, such that the product of R and Q produces matrix H. A second variable transformation part column-swaps matrix H to form H?, thereafter generating Q? and R? subject to the same constraints as was described for Q and R. Transformed variables Z and Z? are formed by multiplying Y by QH and Q?H, respectively. A reduced complexity maximum likelihood decoder has a first part which accepts Z and R and forms a first metric table having entries of all possible x2 accompanied by estimates of x1 derived from x2 and Z, and also including a distance metric.

Abstract: A receive filter for a stream of OFDM symbols has an infinite impulse response (IIR) filter which receives packets having a preamble part followed by a data part, the data part having a succession of cyclic prefixes followed by OFDM symbols. The packet is provided to the IIR filter, and the registers of the IIR filter are reset before or during each cyclic prefix. The IIR filter may be formed from registers which are coupled to return a value to a predecessor register, or as an array of registers, such as in a BIQUAD configuration, where the registers are reset by a shared reset signal.

Abstract: A transmit filter for a stream of OFDM symbols has a remapper, Infinite Impulse Response (IIR) filter and a controller, the transmit filter operating on a stream of OFDM symbols. The transmit filter accepts symbols to be transmitted, the re-mapper re-orders them, the IIR filters the re-ordered stream, and a controller provides an output by rearranging the filtered symbols. The incoming symbol stream contains a series of symbols, each followed by a guard interval, where each guard interval has a first Tg symbol interval, and a second Tg symbol interval, the remapper generating a re-ordered stream having a first Tg symbol interval, a second Tg symbol interval and the symbol, the output of the IIR filter thereby generating a filtered first Tg symbol, a filtered second Tg symbol, and a filtered symbol, and the controller forms the transmit output by discarding the filtered first Tg symbol and outputting, in sequence, the filtered second Tg symbol, the filtered symbol, and a copy of the filtered second Tg symbol.

Abstract: An packet detection controller accepts an input from an AGC controller which indicates the presence of an increased signal energy and also completion of an AGC process and generates an output to suspend the AGC process. The packet detection controller also receives a plurality of IQ receiver streams and forms a single stream for use by a packet detector, which is controllable by an SNR_MODE indicating whether the signal to noise ratio is above or below a particular threshold, and a PD_RESET signal indicating that no packet detection should occur. The controller also receives a PACKET_DET signal indicating that packet detection is completed. The packet detection controller examines the incoming receiver streams and suspends AGC process if a packet detect is generated, or suspends the packet detector if an AGC process is required.

Abstract: A re-transmit processor for a wireless communication system includes a pointer memory which contains pointers associated with particular packet data in a host memory. The re-transmit processor directs data associated with the pointers to be applied to a media access controller, which optionally contains an encryption function, the output of which is coupled to a block buffer and to an output interface. Upon receipt of a transmission request, the host memory locations associated with the pointers are read and the data directed to the media access controller, which adds a header, a CRC, and optionally encrypts the data, thereafter placing it in the block buffer and the output interface. Upon provision of the packet data to the MAC, the associated pointer is initialized to a FREE or UNUSED value, and upon receipt of an acknowledgement of the packet accompanied by a packet identifier from a receiving station, the packet associated with the packet identifier is removed from the block buffer.

Abstract: An packet detection controller accepts an input from an AGC controller which indicates the presence of an increased signal energy and also completion of an AGC process and generates an output to suspend the AGC process. The packet detection controller also receives a plurality of IQ receiver streams and forms a single stream for use by a packet detector, which is controllable by an SNR_MODE indicating whether the signal to noise ratio is above or below a particular threshold, and a PD_RESET signal indicating that no packet detection should occur. The controller also receives a PACKET_DET signal indicating that packet detection is completed. The packet detection controller examines the incoming receiver streams and suspends AGC process if a packet detect is generated, or suspends the packet detector if an AGC process is required.

Abstract: A preamble detector for a plurality of streams of baseband digitized signals has a plurality of preamble processors, each preamble processor coupled to an input and generating an output. Each preamble processor has an input coupled to a first delay, the output of the first delay coupled to a second delay generating an output. The first and second delay are substantially equal to a preamble part. A first multiplier generates an output from a conjugated output of the second delay output and a first delay output. A second multiplier generates an output from a conjugated first delay output and an input stream. The first and second multiplier outputs are accumulated over an interval, and the complex output of the accumulator is formed into a magnitude, thereby generating the output of each preamble processor. The outputs of the preamble processors are summed and compared to a threshold to generate a preamble detect.

Abstract: A process for equalizing streams of OFDM subcarrier data computes the noise variance for each stream, and forms a stream weighting coefficient by equalizing the noise variance, such that for a first stream having a noise variance ?1 and a second stream having a noise variance of ?2, the first stream is scaled by k 1 = 2 ? ? 2 ? 1 2 + ? 2 2 and the second stream is scaled by k 2 = 2 ? ? 1 ? 1 2 + ? 2 2 .

Abstract: An packet detection controller accepts an input from an AGC controller which indicates the presence of an increased signal energy and also completion of an AGC process and generates an output to suspend the AGC process. The packet detection controller also receives a plurality of IQ receiver streams and forms a single stream for use by a packet detector, which is controllable by an SNR_MODE indicating whether the signal to noise ratio is above or below a particular threshold, and a PD_RESET signal indicating that no packet detection should occur. The controller also receives a PACKET_DET signal indicating that packet detection is completed. The packet detection controller examines the incoming receiver streams and suspends AGC process if a packet detect is generated, or suspends the packet detector if an AGC process is required.

Abstract: An packet detection controller accepts an input from an AGC controller which indicates the presence of an increased signal energy and also completion of an AGC process and generates an output to suspend the AGC process. The packet detection controller also receives a plurality of IQ receiver streams and forms a single stream for use by a packet detector, which is controllable by an SNR_MODE indicating whether the signal to noise ratio is above or below a particular threshold, and a PD_RESET signal indicating that no packet detection should occur. The controller also receives a PACKET_DET signal indicating that packet detection is completed. The packet detection controller examines the incoming receiver streams and suspends AGC process if a packet detect is generated, or suspends the packet detector if an AGC process is required.

Abstract: A transmit power allocation method for computing a transmit beamforming W matrix for a N streams of data, the method has a first step of measuring a receive channel characteristic H matrix, a second step of decomposing the H matrix into a U matrix which is formed from the left eigenvectors of the H matrix, an ? matrix which is a diagonal matrix formed from the square roots of the eigenvalues of said H matrix and re-ordered by strength, and a VT matrix with rows comprising the right eigenvectors of H, such that U?VT=H. The transmit beamforming W matrix is then formed from the re-ordered V matrix of the previous decomposition. Optional waterfilling methods for a plurality of subcarriers may then be done using either a minimum mean square error, an optimal signal to noise ratio, or any other waterfilling method which optimizes a desired metric, such as signal to noise ratio or minimum mean square error.

Abstract: A wireless signal processor for use in identifying a maximum Carrier to Noise Interference Ratio (CINR) associated with a plurality of received OFDMA subcarriers has a candidate generator for forming a plurality of candidate values from a particular set of received subcarriers by forming candidate values based on the received subcarriers in combination with possible integer preamble offsets and possible preamble values. A candidate evaluator selects which of the possible preamble values and integer frequency offset values have the maximum CINR, and provides the maximum CINR with IFO and preamble index as outputs.

Abstract: A gain controller for a wireless communication system sets the receiver gain during the initial time duration of a preamble, and for each subsequent symbol computes a new gain value, which is applied at the end of each symbol. An analog to digital converter resolution controller sets the resolution of the ADC to a high resolution during a preamble interval and a first symbol interval, and to a comparatively lower resolution thereafter until the end of the frame. When a new zone is entered, the first symbol of the new zone is sampled at a higher resolution than the subsequent symbols.

Abstract: An apparatus and a process for transferring packet data includes receiving packets from a first interface such as a network interface and transferring data to a second interface such as an SD Bus interface such as SDIO using a protocol such as one described in SDCard.org. The SD Bus second interface operates as a slave device to a master device, and the packet transfer from first interface to second interface includes concatenating length fields and packet data fields from packets received on the first interface to form a superframe which is provided to the second interface at time of data transfer. The formation of each superframe includes starting a timer such that the superframe is transmitted to the second interface by asserting an interrupt on that interface when either the timer expires, the number of packet from the first interface exceeds a threshold, or the amount of data from the first interface exceeds a threshold.

Abstract: A process for equalizing streams of OFDM subcarrier data computes the noise variance for each stream, and forms a stream weighting coefficient by equalizing the noise variance, such that for a first stream having a noise variance ?1 and a second stream having a noise variance of ?2, the first stream is scaled by k 1 = 2 ? ? 2 ? 1 2 + ? 2 2 and the second stream is scaled by k 2 = 2 ? ? 1 ? 1 2 - ? 2 2 .