Abstract: Apparatuses and methods for operating a power converter are described. An integrated circuit can be integrated in a high-side driver of a high-side fiend-effect transistor (FET) of the power converter. The integrated circuit can detect a phase node voltage of a power integrated circuit. The integrated circuit can, in response to the phase node voltage being less than a threshold voltage, operate a high-side FET of the power integrated circuit in a constant-current mode. The integrated circuit can, in response to the phase node voltage being greater than the threshold voltage, operate the high-side FET of the power integrated circuit in a constant-voltage mode.

Abstract: A method of controlling a multilevel power converter may include measuring an input voltage at a converter input, determining a half input voltage based on the input voltage; measuring a flying capacitor voltage across the flying capacitor; determining an error voltage based on a difference between the flying capacitor voltage and the half input voltage; generating an inductor current window having an inductor peak current and a valley inductor current; modulating the inductor peak current into an upper inductor peak current and a lower inductor peak current based on the error voltage; and operating the multilevel power converter to produce an output current through an inductor to a converter output, the output current being within the inductor current window and based on a sequence of pulse width modulation states.

Abstract: A switching converter with adjustable on-time is presented. The switching converter includes an inductor coupled to a power switch; a pulse generator generating a pulsed signal to switch the power switch and a controller. The pulsed signal has an on-time adjustable between a first value and a second value, the first value being shorter than the second value. The controller identifies a mode of operation between a continuous conduction mode and a discontinuous conduction mode and sets the on-time to the second value when a continuous conduction mode is identified. The controller also measures a duration between successive inductor current pulses, compares the duration with a first threshold value and maintains the on-time to the second value as long as the duration is less than the first threshold value. When the duration increases above the first threshold value the controller sets the on-time to the first value.

Abstract: A switched-mode power supply, such as a constant on time regulator, is presented. The switched-mode power supply includes a high side power switch coupled to a low side power switch at a switching node. A ramp injection circuit is coupled to the switching node and a ramp switch is coupled to the ramp injection circuit are also provided. A driver is used to drive the high side power switch and the low side power switch and to control the ramp switch. The driver turns off the ramp switch when the switch-mode power supply enters a tri-state, and turns the ramp switch back on when the switch-mode power supply exists the tri-state. The tri-state occurs when the switched-mode power supply operates in a discontinuous current mode, when both the high side power switch and the low side power switch are turned off.

Abstract: Systems and methods for detecting a plunger movement condition with respect to a solenoid coil are described. A method may include generating a first derivative signal waveform of a current flowing in the solenoid coil, identifying whether there is at least one zero crossing point in the first derivative signal waveform, and detecting the plunger movement condition according to an identification result indicating whether there is at least one zero crossing point in the first derivative signal waveform.

Abstract: Systems and methods for operating a voltage converter are described. A circuit can multiply a digital code by a predetermined multiplier to obtain a product. The digital code can represent a desired output voltage of the voltage converter. The predetermined multiplier can cause the product to be maintained within a predetermined window. The product can be maintained within the predetermined window to cause an output of a reference digital-to-analog converter of the voltage converter to be maintained within a predetermined voltage window. The circuit can receive a feedback voltage indicating an output voltage of the voltage converter. The circuit can divide the feedback voltage by a divisor to obtain a divided voltage. The divisor can correspond to the digital code. The circuit can send the divided voltage to an error amplifier of the voltage converter.

Abstract: Apparatuses, devices, and methods for operating a multi-level voltage converter are described. A semiconductor device can include a circuit, where the circuit can include a plurality of current sources. The circuit can be configured to measure a flying capacitor voltage across a flying capacitor of a multi-level voltage converter. The circuit can be further configured to compare the flying capacitor voltage with a voltage level equivalent to an intermediate voltage that is between ground and an input voltage being provided to the multi-level voltage converter. The circuit can be further configured to, based on a result of the comparison, switch a current source among the plurality of current sources to maintain the flying capacitor voltage at the intermediate voltage.

Abstract: Methods and systems for operating a multiphase voltage regulator are described. The multiphase voltage regulator can include a plurality of power stages. A controller can be connected to the plurality of power stages. The controller can detect a number of activated power stages among the plurality of power stages. The controller can adjust a gain of a current sense feedback loop of the controller to control a load-transient response of the multiphase voltage regulator. The adjustment to the gain can be based on the number of activated power stages.

Abstract: Systems, devices, and methods for isolating digital signals are described. A carrier signal can be modulated using a first signal to generate a first modulated signal. The carrier signal and the first modulated signal can be transmitted through a forward path in an isolation barrier, where transmitting the carrier signal through the isolation barrier can transform the carrier signal into a delayed carrier signal. The first modulated signal can be demodulated to recover the first signal. The delayed carrier signal can be modulated using a second signal to generate a second modulated signal. The delayed carrier signal and the second modulated signal can be transmitted through a return path in the isolation barrier, where the return path and the forward path has opposite directions.

Abstract: An inductive position sensor including at least one transmit coil, an absolute position receive coil pair, a high-resolution position receive coil pair and a conductive moving target, the absolute position receive coil pair and the high-resolution receive coil pair together define a measurement area of the inductive position sensor and the moving target can move in this measurement area, the absolute position coil pair has a first sine receive coil and a first cosine receive coil, both having one period over the measurement area of the inductive position sensor, the high-resolution position receive coil pair has a second sine receive coil and a second cosine receive coil, both having at least two periods over the measurement area of the inductive position sensor, the absolute position receive coil pair and the high-resolution position receive coil pair are arranged in the same area of a printed-circuit board of the inductive position sensor.

Abstract: An authentication method for authenticating a wireless power transmitter to a wireless power receiver includes receiving a SSP value, an ID, and a random number RND from a wireless power receiver; determining an index based on the RND; choosing a base code from a set of base codes according to the index; determining a secure code from the base code, the index, the RND, the SSP value, and the ID; and transmitting the secure code to the wireless power receiver. A further method includes receiving a secure code from the wireless power transmitter; retrieving an index from the secure code; determining a base code from a set of base codes according to the index; calculating a second secure code; and authenticating the wireless power transmitter by comparing the secure code and the second secure code.

Abstract: A circuit and corresponding method for determining a delay are presented. The circuit includes a delay circuit, a feedback circuit and a controller. The delay circuit receives an input signal having an input edge and provides an output signal having an output edge. The input edge and the output edge are separated by a delay. The feedback circuit causes the delay circuit to generate a series of consecutive output pulses. The controller sets the delay to a first delay value and measures a first period of output pulses; sets the delay to a second delay value and measure a second period of output pulses. The controller then calculates the delay based on a difference between the first period and the second period.

Abstract: In an embodiment, an apparatus is disclosed that includes a power management integrated circuit (PMIC). The PMIC includes a voltage regulator supplied by a first power source and configured to generate a first output and a charge pump supplied by a second power source and configured to generate a second output. A bias voltage output of the power management integrated circuit is generated based at least in part on the first output and the second output. The charge pump is configured to adjust the second output based at least in part on a comparison between the bias voltage output and a reference voltage.

Abstract: In an embodiment, a semiconductor device is disclosed that includes a wired input/output, a wireless input/output, and a battery. A wired charging path between the wired input/output and the battery includes a first transistor and a second transistor. A wireless charging path between the wireless input/output and the battery includes a third transistor and the second transistor.

Abstract: Apparatuses including a coil and methods of forming the coil are described. The coil can include a first coil layer including at least an inner strand and an outer strand. The coil can further include a second coil layer including at least an inner strand and an outer strand. The inner strand of the first coil layer can be connected to the outer strand of the second coil layer. The outer strand of the first coil layer can be connected to the inner strand of the second coil layer.

Abstract: A correction circuit for correcting an amplitude imbalance and a phase imbalance between an in-phase signal and a quadrature signal, the correction circuit comprising a plurality of variable gain circuits configured to provide in-phase and quadrature signals having balanced amplitudes and balanced phases, wherein each variable gain circuit is configured to apply a gain to amplify, attenuate or to pass a signal.

Abstract: A method for detecting a phase shift in an output signal of an inductive position sensor by calculating the phase spectrum of the position signal based on a Fast Fourier Transformation of the position signal and comparing the calculated phase spectrums over time to detect changes in the phase spectrums.

Abstract: Semiconductor devices for synchronizing networks are described. A semiconductor device can include an analog phase-lock loop (APLL) configured to output a first signal. The semiconductor device can further include a first digital phase-lock loop (DPLL) configured to output a second signal. The semiconductor device can further include a second DPLL configured to output a third signal. A combination of the first signal and the second signal can be used to generate a first output clock signal. A difference resulting from a subtraction of the second signal from the third signal can be used to generate a second output clock signal.

Abstract: Semiconductor devices for driving transistors in a power device are described. A semiconductor device can include a voltage source configured to provide a fixed bias voltage to a first device implemented as a common gate device. The semiconductor device can further include a second device connected in series with the first device. The current output of the second device can be connected to a source terminal of the first device. The semiconductor device can further include a driver configured to drive the second device to perform current control on the first device.

Abstract: According to certain general aspects, the present embodiments relate generally to securing communication between ECUs. Example implementations can include a method of securely transmitting Controller Area Network (CAN) protocol frames via a CAN controller.