Patents Assigned to Renesas Technology
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Patent number: 7561095Abstract: A semiconductor integrated circuit device provided with a pipeline A-D conversion circuit in which the enhancement of accuracy and the reduction of power consumption are accomplished is provided. The pipeline A-D conversion circuit is connected in series with an input terminal to which an analog signal to be converted is inputted and has a plurality of stages. The stages other than the first stage connected with the input terminal through at least one stage, including the first stage that receives input signals from the input terminal are constructed as follows: each of the other stages is comprised of two or more sample and hold circuits and an amplifier connected in common with the two or more sample and hold circuits. The two or more sample and hold circuits are caused to perform interleave operation.Type: GrantFiled: August 15, 2007Date of Patent: July 14, 2009Assignee: Renesas Technology Corp.Inventors: Fumiyasu Sasaki, Eiki Imaizumi, Takanobu Anbo
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Patent number: 7560975Abstract: The well voltage of a CMOS circuit having low-threshold-voltage MOSFETs is controlled when the power supply is turned on, during normal operation, and when the supply voltage is cut off. The CMOS circuit can thus operate stably with lower power consumption, because latching-up is reduced when the supply voltage is applied to the CMOS circuit or when the supply voltage is cut off, and subthreshold current is decreased during normal operation.Type: GrantFiled: January 5, 2007Date of Patent: July 14, 2009Assignee: Renesas Technology Corp.Inventors: Kiyoo Itoh, Hiroyuki Mizuno
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Patent number: 7562198Abstract: A memory cell mat is divided into a plurality of entries, and an arithmetic logic unit is arranged corresponding to each entry. Between the entries and the corresponding arithmetic logic units, arithmetic/logic operation is executed in bit-serial and entry-parallel manner. Where parallel operation is not very effective, data is transferred in entry-serial and bit-parallel manner to a group of processors provided at a lower portion of the memory mat. In this manner, a large amount of data can be processed at high speed regardless of the contents of operation or data bit width.Type: GrantFiled: June 9, 2005Date of Patent: July 14, 2009Assignee: Renesas Technology Corp.Inventors: Hideyuki Noda, Kazunori Saitoh, Kazutami Ariomoto, Katsumi Dosaka
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Patent number: 7560772Abstract: After silicon oxide film (9) is formed on the surface of a semiconductor substrate (1), the silicon oxide film (9) in a region in which a gate insulation film having a small effective thickness is formed is removed using diluted HF and after that, high dielectric constant insulation film (10) is formed on the semiconductor substrate (1). Consequently, two kinds of gate insulation films, namely, a gate insulation film (12) comprised of stacked film of high dielectric constant insulation film (10) and silicon oxide film (9) and gate insulation film (11) comprised of the high dielectric constant insulation film (10) are formed on the semiconductor substrate (1).Type: GrantFiled: December 23, 2007Date of Patent: July 14, 2009Assignee: Renesas Technology Corp.Inventors: Satoshi Sakai, Atsushi Hiraiwa, Satoshi Yamamoto
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Patent number: 7560910Abstract: There is a need for preventing a MOS transistor from being destroyed due to an inrush current from an input terminal when a boost operation starts from a boost disabling state. During the boost operation, a third MOS transistor (M3) turns off and a fourth MOS transistor (M4) turns on to prevent a current leak from an output terminal (Vout) to an input terminal (Vin) due to a parasitic diode of a second MOS transistor (M2). In the boost disabling state, the third MOS transistor turns on and the fourth MOS transistor turns off to prevent a current leak from the input terminal to the output terminal due to the parasitic diode of the second MOS transistor. When the boost operation starts from the boost disabling state, an electrode toward the output terminal of the second MOS transistor is charged before changing a substrate bias state of this transistor. In this manner, an inrush current is prevented from flowing from the input terminal to the output terminal via the parasitic diode of the second MOS transistor.Type: GrantFiled: September 10, 2007Date of Patent: July 14, 2009Assignee: Renesas Technology Corp.Inventors: Takehiro Hata, Kazuyasu Minami
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Patent number: 7560949Abstract: The testing device is provided with the first element having one end coupled to an input terminal, and the other end coupled to an output terminal, and attenuating a direct-current component, and the second element having one end coupled to the input terminal, and attenuating an alternating current component. The manufacturing method of a semiconductor device includes the step which connects an external output terminal of the semiconductor device, and the input terminal of the testing device, and connects an external input terminal of the semiconductor device, and the output terminal of the testing device, the step which tests the voltage of the other end of the second element, and the step which outputs an alternating current signal to the testing device from the external output terminal of the semiconductor device, and tests the signal which the semiconductor device received in the external input terminal from the testing device.Type: GrantFiled: March 29, 2007Date of Patent: July 14, 2009Assignee: Renesas Technology Corp.Inventor: Hiroshi Noda
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Patent number: 7557034Abstract: For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed.Type: GrantFiled: June 18, 2008Date of Patent: July 7, 2009Assignee: Renesas Technology Corp.Inventors: Katsuhiko Hotta, Kyoko Sasahara
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Patent number: 7558110Abstract: In a SIM card having a flash memory chip, a memory controller chip, and contact/contactless card interfaces, the memory controller chip has a function of executing user authentication of a host equipment, executes processing of data transmitted through the contactless IC card interface (executing reading or writing of data to the flash memory chip) using power supplied from the host equipment to the contact IC card interface, and executes initialization of the flash memory chip between activation of the host equipment and completion of user authentication instructed by the host equipment.Type: GrantFiled: April 27, 2007Date of Patent: July 7, 2009Assignee: Renesas Technology Corp.Inventors: Nagamasa Mizushima, Kunihiro Katayama, Masaharu Ukeda, Yoshinori Mochizuki
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Patent number: 7558106Abstract: An end of a selected bit line in a selected column is electrically coupled to an end of a corresponding current return line by one of first and second write column select gates, which are selectively turned on in response to results of column selection. A data write circuit sets the other end of the selected bit line and the other end of the current return line to one and the other of a power supply voltage and a ground voltage in accordance with a level of write data via one of first and second data buses and an inverted data bus, respectively.Type: GrantFiled: October 10, 2007Date of Patent: July 7, 2009Assignee: Renesas Technology Corp.Inventor: Hideto Hidaka
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Patent number: 7557005Abstract: In a semiconductor device which includes a split-gate type memory cell having a control gate and a memory gate, a low withstand voltage MISFET and a high withstand voltage MISFET, variations of the threshold voltage of the memory cell are suppressed. A gate insulating film of a control gate is thinner than a gate insulating film of a high withstand voltage MISFET, the control gate is thicker than a gate electrode 14 of the low withstand voltage MISFET and the ratio of thickness of a memory gate with respect to the gate length of the memory gate is larger than 1. The control gate and a gate electrode 15 are formed in a multilayer structure including an electrode material film 8A and an electrode material layer 8B, and the gate electrode 14 is a single layer structure formed at the same time as the electrode material film 8A of the control gate.Type: GrantFiled: March 27, 2007Date of Patent: July 7, 2009Assignee: Renesas Technology Corp.Inventors: Yasushi Ishii, Takashi Hashimoto, Yoshiyuki Kawashima, Koichi Toba, Satoru Machida, Kozo Katayama, Kentaro Saito, Toshikazu Matsui
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Patent number: 7558107Abstract: An electrically programmable and erasable non-volatile semiconductor memory such as a flash memory is designed into a configuration in which, when a cutoff of the power supply occurs in the course of a write or erase operation carried out on a memory cell employed in the non-volatile semiconductor memory, the operation currently being executed is discontinued and a write-back operation is carried out to change a threshold voltage of the memory cell in the reversed direction. In addition, the configuration also allows the number of charge-pump stages in an internal power-supply configuration to be changed in accordance with the level of a power-supply voltage so as to make the write-back operation correctly executable. As a result, no memory cells are put in deplete state even in the event of a power-supply cutoff in the course of a write or erase operation.Type: GrantFiled: October 5, 2007Date of Patent: July 7, 2009Assignee: Renesas Technology Corp.Inventors: Ryotaro Sakurai, Hitoshi Tanaka, Satoshi Noda, Koji Shigematsu
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Patent number: 7556916Abstract: A resist film is applied to an entire surface and subjected to patterning substantially in the same form as an opening to bury the resist film inside the opening. When a positive resist is used, a photomask having a light-shielding portion with an area smaller than the opening is used in patterning. When a negative resist is used, a photomask having a light transmitting portion with an area smaller than the opening is used.Type: GrantFiled: November 6, 2007Date of Patent: July 7, 2009Assignee: Renesas Technology Corp.Inventor: Sachiko Hattori
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Patent number: 7557809Abstract: The basic section of the multimedia data-processing system includes a CPU 1100, an image display unit 2100, a unified memory 1200, a system bus 1920, and devices 1300, 1400, and 1500 connected to the system bus. In this configuration, the CPU is formed on an LSI mounted on a single silicon wafer including instruction processing unit 1110 and display control unit 1140. Main storage area 1210 and display area 1220 are stored within the unified memory. Unified memory port 1910 for connecting the corresponding LSI and the unified memory is provided independently of the system bus intended to connect the LSI and the input/output devices. The unified memory port can be driven faster than system bus.Type: GrantFiled: November 9, 2004Date of Patent: July 7, 2009Assignee: Renesas Technology Corp.Inventors: Yasuhiro Nakatsuka, Tetsuya Shimomura, Manabu Jyou, Yuichiro Morita, Takashi Hotta, Kazushige Yamagishi, Yutaka Okada
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Patent number: 7557427Abstract: A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction; a plurality of second interconnections each adjacent to the first interconnection located at an edge of the capacitance forming region, extending in the predetermined direction, and having a fixed potential; and an insulating layer formed on the main surface and filling in between each of the first interconnections and between the first interconnection and the second interconnection adjacent to each other. The first interconnections and the second interconnections are located at substantially equal intervals in a plane parallel to the main surface, and located to align in a direction substantially perpendicular to the predetermined direction.Type: GrantFiled: August 27, 2007Date of Patent: July 7, 2009Assignees: Renesas Technology Corp., Renesas Device Design Corp.Inventors: Takashi Okuda, Yasuo Morimoto, Yuko Maruyama, Toshio Kumamoto
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Patent number: 7558944Abstract: A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and 7.Type: GrantFiled: March 7, 2008Date of Patent: July 7, 2009Assignee: Renesas Technology Corp.Inventors: Hiroshi Ohsuga, Atsushi Kiuchi, Hironobu Hasegawa, Toru Baji, Koki Noguchi, Yasushi Akao, Shiro Baba
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Patent number: 7557436Abstract: Wiring lines for the supply of a voltage to feed a drive voltage to an integrated circuit formed in a semiconductor chip are disposed so as to cover a main surface of the semiconductor chip, so that, if the wiring lines are removed for the purpose of analyzing information stored in the semiconductor chip, the integrated circuit does not operates and it is impossible to analyze the information. Further, there is provided a processing detector circuit for detecting that the wiring lines have been tampered with. When the processing detector circuit detects a change in the sate of the wiring lines, the integrated circuit is reset. Thus, it is possible to improve the security of information stored on the card.Type: GrantFiled: November 1, 2006Date of Patent: July 7, 2009Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Hirotaka Mizuno, Yoshio Masumura, Takeo Kon, Yukio Kawashima
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Patent number: 7556997Abstract: In formation of a source/drain region of an NMOS transistor, a gate-directional extension region <41a> of an N+ block region <41> in an N+ block resist film <51> prevents a well region <11> located under the gate-directional extension region <41a> from implantation of an N-type impurity. A high resistance forming region, which is the well region <11> having a possibility for implantation of an N-type impurity on a longitudinal extension of a gate electrode <9>, can be formed as a high resistance forming region <A2> narrower than a conventional high resistance forming region <A1>. Thus, a semiconductor device having a partially isolated body fixed SOI structure capable of reducing body resistance and a method of manufacturing the same are obtained.Type: GrantFiled: October 18, 2007Date of Patent: July 7, 2009Assignee: Renesas Technology Corp.Inventors: Shigenobu Maeda, Toshiaki Iwamatsu, Takashi Ipposhi
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Patent number: 7554872Abstract: In order to implement a memory having a large storage capacity and a reduced data retention current, a non-volatile memory, an SRAM, a DRAM, and a control circuit are modularized into one package. The control circuit conducts assignment of addresses to the SRAM and DRAM, and stores data that must be retained over a long period of time in the SRAM. In the DRAM, a plurality of banks are divided into two sets, and mapped to the same address space, and sets are refreshed alternately. A plurality of chips of them are stacked and disposed, and wired by using the BGA and chip-to-chip bonding.Type: GrantFiled: January 19, 2005Date of Patent: June 30, 2009Assignee: Renesas Technology Corp.Inventors: Kazushige Ayukawa, Seiji Miura, Yoshikazu Saitou
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Patent number: 7554202Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.Type: GrantFiled: July 27, 2007Date of Patent: June 30, 2009Assignee: Renesas Technology CorpInventors: Yasushi Koubuchi, Koichi Nagasawa, Masahiro Moniwa, Youhei Yamada, Toshifumi Takeda
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Patent number: 7554181Abstract: The present invention provides a non-insulated type DC-DC converter having a circuit in which a power MOS•FET for a high side switch and a power MOS•FET for a low side switch are connected in series. In the non-insulated type DC-DC converter, the power transistor for the high side switch, the power transistor for the low side switch, and driver circuits that drive these are respectively constituted by different semiconductor chips. The three semiconductor chips are accommodated in one package, and the semiconductor chip including the power transistor for the high side switch, and the semiconductor chip including the driver circuits are disposed so as to approach each other.Type: GrantFiled: February 9, 2005Date of Patent: June 30, 2009Assignee: Renesas Technology Corp.Inventors: Yukihiro Satou, Tomoaki Uno, Nobuyoshi Matsuura, Masaki Shiraishi