Patents Assigned to Renesas Technology
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Patent number: 7215179Abstract: The present invention relates to a booster circuit of a non-volatile memory requiring a plus or minus high voltage equal to or higher than a power-supply voltage. The present invention can generate a high voltage of approximately 12 V even at a low power-supply voltage equal to or lower than 3 V and generate not only a plus high voltage but also a minus high voltage by the same circuit. Also, by combining a body-controlled type parallel charge pump, which is a booster circuit according to the present invention, with a serial-type charge pump, two types of high voltages can be efficiently generated and a reduction in chip areas can be achieved.Type: GrantFiled: September 26, 2003Date of Patent: May 8, 2007Assignee: Renesas Technology Corp.Inventors: Takanori Yamazoe, Takeo Kanai
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Patent number: 7216193Abstract: It is aimed at improving the efficiency of data transfer processing and the concurrent data processing on a central processing unit. A data transfer device can independently request a bus access right and output an address to a first bus (IBUS) and a second bus (PBUS). It is possible to solve the state of competing for the bus access right between both buses. While the bus access right of one bus is granted for reading or writing, the bus access right of the other bus can be released. When the data transfer device releases the bus access right for the first bus, a central processing unit can process data. In response to one data transfer start request, the bus access right is requested for one bus and the other bus, There is not used a sequence of requesting the bus access right in response to different data transfer requests for respective buses. It is possible to simplify a handshake sequence of a data transfer request and its acknowledgment.Type: GrantFiled: June 28, 2006Date of Patent: May 8, 2007Assignee: Renesas Technology Corp.Inventor: Naoki Mitsuishi
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Patent number: 7215203Abstract: A multistage high frequency power amplifier-circuit device has a plurality of semiconductor amplification elements connected in a cascade. The circuit device is provided with a bias control circuit used to control the bias voltage or bias current of the output semiconductor amplification element in each stage so as to reduce the variation of the output power with respect to the power control signal voltage in an area around the threshold voltage of the semiconductor amplification elements. This realizes a high frequency power amplifier circuit device provided with excellent controllability of the output power and high efficiency at the time of low power output realized with use of such a control voltage as a power control signal.Type: GrantFiled: May 1, 2006Date of Patent: May 8, 2007Assignees: Renesas Technology Corp., Hitachi Communication Systems, Inc.Inventors: Yoshikuni Matsunaga, Toshihiko Shimizu, Tomio Furuya, Nobuhiro Matsudaira, Koichi Matsushita
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Patent number: 7214558Abstract: Provided is a technique of improving the properties of a bipolar transistor. Described specifically, upon formation of a collector electrode around a base mesa by the lift-off method, a resist film is formed over connection portions between the outer periphery of a region OA1 and a region in which the base mesa 4a is formed, followed by successive formation of gold germanium (AuGe), nickel (Ni) and Au in the order of mention over the entire surface of a substrate so that the stacked film of them will not become an isolated pattern. As a result, the stacked film over the base mesa 4a is connected to a stacked film at the outer periphery of the region OA1, facilitating peeling of the stacked film over the base mesa 4a. In addition, generation of side etching upon formation of a via hole extending from the back side of the substrate to a backside via electrode is reduced by forming the backside via electrode using a material such as WSi which hardly reacts with an n type GaAs layer or n type InGaAs layer.Type: GrantFiled: October 25, 2005Date of Patent: May 8, 2007Assignee: Renesas Technology Corp.Inventors: Atsushi Kurokawa, Hiroshi Inagawa, Toshiaki Kitahara, Yoshinori Imamura
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Publication number: 20070099406Abstract: In a semiconductor device manufacturing method of the invention, a metal film, for forming a gate electrode, is formed on a gate insulating film. Subsequently, when the metal film is processed, part of the metal film is removed by a wet etching process using a given chemical liquid.Type: ApplicationFiled: October 23, 2006Publication date: May 3, 2007Applicant: Renesas Technology Corp.Inventors: Masahiko Higashi, Satoshi Kume, Jiro Yugami, Shinichi Yamanari, Takahiro Maruyama, Itaru Kanno
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Patent number: 7212047Abstract: A semiconductor integrated circuit having a built-in PLL circuit which has two charge pump circuits for charging and discharging capacitive elements of a loop filter in response to signals generated by a phase comparator circuit. One of the two charge pump circuits has current sources which generate current values smaller than those generated by current sources of the other charge pump circuit. The loop filter has a first capacitive element connected to a charge/discharge node, and a second capacitive element connected to the charge/discharge node through a resistive element. The first capacitive element is charged and discharged by the one charge pump circuit, while the second capacitive element is charged and discharged by the other charge pump circuit. A charging current source of the one charge pump circuit operates simultaneously with a discharging current source of the other charge pump circuit, i.e., the charge pump circuits operate in opposite phase.Type: GrantFiled: October 4, 2005Date of Patent: May 1, 2007Assignees: Renesas Technology Corp., Epoch Microelectronics, Inc.Inventors: Yasuyuki Kimura, Satoshi Shimizu, Masakatsu Yokota, Ken Suyama, Aleksander Dec
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Patent number: 7211892Abstract: In order to inhibit the connection failure due to the degradation of the connection interface strength of the electrode pad and the warp thereof in the semiconductor device having an electrode pad, a metal layer formed on the electrode pad, and a metal bump formed on the metal layer, in the present invention, gold (Au) is contained in the metal layer, the metal bump is made of solder mainly made of Sn and designed to have an average height H of 100 ?m or less per unit area in the electrode pad, and the concentration of Au of the metal layer dissolved in the solder is set to 1.3Ć10?3 (Vol %) or less. More preferably, the metal bump contains palladium (Pd), and the solder coating for forming the metal bump on the electrode pad is performed by using the dipping and the paste printing in combination.Type: GrantFiled: June 7, 2005Date of Patent: May 1, 2007Assignee: Renesas Technology Corp.Inventors: Shiro Yamashita, Yoichi Abe, Kenichi Yamamoto, Ryosuke Kimoto, Hiroshi Kawakubo
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Patent number: 7212441Abstract: In a nonvolatile semiconductor memory device, the increase of the capacity of a nonvolatile semiconductor memory inevitably causes the power supply circuits including the charge pump circuits at the periphery to increase. In view of the above situation, the object of the present invention is to provide a technology of allowing a nonvolatile semiconductor memory to increase the capacity without increasing the power supply circuits which are the peripheral circuits of the nonvolatile semiconductor memory.Type: GrantFiled: November 15, 2005Date of Patent: May 1, 2007Assignee: Renesas Technology CorporationInventors: Takanori Yamazoe, Shin Ito, Yoshiki Kawajiri
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Patent number: 7211903Abstract: A semiconductor device which can meet the requirement for a further increase in pins, which multi-functionalization and faster operation would entail is to be provided. Bonding pads and bonding pads are arranged in a zigzag pattern in a direction along an outer circumference of a main surface of a chip. To focus on power supply-line bonding pads among all the bonding pads, an odd number of bonding pads are to be arranged in a direction of the outer circumference of the main surface between adjoining bonding pads. A greater width is secured for the power supply-line bonding pads than for other bonding pads, and a diameter of wires to be connected to the power supply-line bonding pads is set greater than that of other wires.Type: GrantFiled: December 7, 2004Date of Patent: May 1, 2007Assignee: Renesas Technology Corp.Inventors: Yoshinori Miyaki, Kazunari Suzuki, Hirohito Ohashi
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Patent number: 7211862Abstract: A semiconductor device wherein an avalanche withstand of power MISFET is improved without enlarging cell pitch. In the semiconductor device, impurity ions having a p-type conduction, e.g. B ions, are introduced from a bottom of a contact hole to form a p-type semiconductive region that is provided below a p+-type semiconductive region and in contact with the p+-type semiconductive region and an n?-type single crystal silicon layer and that has an impurity concentration lower than the p+-type semiconductive region. An n-type semiconductive region is formed in the n?-type single crystal silicon layer provided below the p-type semiconductive region as being in contact with the p-type semiconductive region and has an impurity concentration lower than the n?-type single crystal silicon layer.Type: GrantFiled: October 14, 2005Date of Patent: May 1, 2007Assignee: Renesas Technology Corp.Inventors: Yoshito Nakazawa, Yuji Yatsuda
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Patent number: 7212027Abstract: Provided is a disconnection and short detecting circuit capable of detecting disconnection and short of a signal line transmitting a differential clock signal. A differential buffer part DB1 has a first comparator to compare a non-inverting clock signal inputted from a PADI and an inverting clock signal inputted from a PADR; a second comparator to compare a non-inverting clock signal and a reference potential Vref; and a third comparator to compare an inverting clock signal and the reference potential Vref. Their respective outputs are defined as Y, YI and YR, respectively. If the signal line of either a non-inverting clock signal or an inverting clock signal is disconnected, or short-circuited to a grounding potential VSS of a logical value Low, the logical values outputted from the second and the third comparators are equal for a long period of time in one cycle of the non-inverting clock signal or the inverting clock signal.Type: GrantFiled: July 28, 2004Date of Patent: May 1, 2007Assignee: Renesas Technology Corp.Inventors: Atsuhiko Ishibashi, Yasuhiro Fujino
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Patent number: 7213217Abstract: There are saved layout data which have parent cell information indicative of higher order cell data to directly refer to low order cell data (or basic element data), thereby defining a reverse hierarchical structure. More specifically, both of basic element data (figD1 and figD2) have cell data (cell2) as the parent cell information, all of basic element data (figD3 to figD5) have cell data (cell3) as the parent cell information, the cell data (cell3) have two identical cell data (cell2 and cell2) as the parent cell information, and the cell data (cell2) have three identical cell data (cell3, cell3 and cell3) as the parent cell information.Type: GrantFiled: August 4, 2005Date of Patent: May 1, 2007Assignee: Renesas Technology Corp.Inventor: Kazuya Kamon
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Patent number: 7212425Abstract: A nonvolatile storage element of a single-layer gate type structure is arranged so that a floating gate is formed of a conductive layer which partly overlaps with a control gate, formed of a diffused layer, and is provided with a barrier layer covering a part of or the whole surface of the floating gate. Nonvolatile storage elements characterized as such are used for redundancy control of defects or change of functions.Type: GrantFiled: September 19, 2005Date of Patent: May 1, 2007Assignees: Renesas Technology Corp., Hitachi Ulsi Systems Co., Ltd.Inventors: Kenichi Kuroda, Toshifumi Takeda, Hisahiro Moriuchi, Masaki Shirai, Jiroh Sakaguchi, Akinori Matsuo, Shoji Yoshida
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Patent number: 7212786Abstract: Providing a wireless communication device that, even if clock stop of a radio frequency part is controlled by a baseband part operating on the same clock signal, can resume clock oscillation, and makes it easy to time the clock reactivation to other operations based on a shared clock. The wireless communication device comprises an RF part generating a first clock signal and a baseband part. The baseband part generates a second clock signal, controls the generation and stop of the first clock signal, uses the first clock signal to perform data processing and a clocking operation, and in a low power consumption state in which the first clock signal is stopped, uses the second clock signal to perform a timer operation and a clocking operation. The generation timing of the first clock signal can be generated by the timer operation using the second clock signal.Type: GrantFiled: April 10, 2003Date of Patent: May 1, 2007Assignee: Renesas Technology CorporationInventors: Hirotsugu Kojima, Atsushi Kiuchi, Yuichi Takitsune, Katsumi Yamamoto
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Patent number: 7211857Abstract: A non-volatile semiconductor memory device includes a semiconductor substrate, an insulating film formed on the semiconductor substrate, a plurality of memory cells formed on the semiconductor substrate, a plurality of first assist gates extending toward the memory cell, a connection portion connecting end portions of the first assist gates, a second assist gate extending toward the memory cell, a first select transistor controlling whether to apply a voltage to an area under the first assist gate, a second select transistor controlling whether to apply a voltage to an area under the second assist gate, and an impurity region. The insulating film formed under an intersection area of the connection portion and the impurity region has a thickness larger than the insulating film formed under the first and second assist gates. A non-volatile semiconductor memory device capable of ensuring a writing speed as well as reliability can thus be obtained.Type: GrantFiled: October 25, 2005Date of Patent: May 1, 2007Assignee: Renesas Technology Corp.Inventors: Yoshihiro Ikeda, Hiroshi Ishida
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Patent number: 7211497Abstract: According to the present invention, an oxide film with the film quality almost equivalent to that of the thermal oxide can be formed by the low-temperature treatment. After removing an insulator on the active region of the substrate which constitutes a semiconductor wafer, an insulator made of, for example, silicon oxide is deposited on the main surface of the semiconductor wafer by the low pressure CVD method. This insulator is a film to form a gate insulator of MISFET in a later step. Subsequently, a plasma treatment is performed in an atmosphere containing oxygen (oxygen plasma treatment) to the insulator in the manner as schematically shown by the arrows. By so doing, the film quality of the insulator formed by the CVD method can be improved to the extent almost equivalent to that of the insulator formed of the thermal oxide.Type: GrantFiled: October 30, 2003Date of Patent: May 1, 2007Assignee: Renesas Technology Corp.Inventors: Atsushi Hiraiwa, Satoshi Sakai, Dai Ishikawa, Yoshihiro Ikeda
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Patent number: 7212444Abstract: An operation scheme for operating stably a semiconductor nonvolatile memory device is provided. When hot-hole injection is conducted in the semiconductor nonvolatile memory device of a split gate structure, the hot-hole injection is verified using a crossing point that does not change with time. Thus, an erased state can be verified without being aware of any time-varying changes. Also, programming or programming/erasure is conducted by repeating pulse voltage or multi-step voltage application to a gate section multiple times.Type: GrantFiled: May 26, 2005Date of Patent: May 1, 2007Assignee: Renesas Technology Corp.Inventors: Digh Hisamoto, Kan Yasui, Tetsuya Ishimaru, Shinichiro Kimura, Daisuke Okada
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Patent number: 7212744Abstract: The invention provides a transceiver circuit for communication that enhances the operation frequency of a synchronous digital circuit up to the maximum frequency of a flip-flop and inhibits the occurrence of jitters. A clock signal synchronized with data at f1/n Hz is converted by a multiplier so that the signal has a frequency of ānā times so as to use the clock signal for triggering a flip-flop the operation frequency of which is f1 b/s in the synchronous digital circuit. The multiplier is arranged in the vicinity of the flip-flop triggered by the clock signal of f1 Hz so as to avoid the effect of the deterioration of the operation frequency by interconnect capacitance. The maximum operation frequency of the transceiver circuit determined based upon the operating frequency of the synchronous digital circuit can be enhanced up to the maximum operation frequency of the flip-flop.Type: GrantFiled: January 20, 2004Date of Patent: May 1, 2007Assignee: Renesas Technology CorpInventors: Nobuhiro Shiramizu, Kenichi Ohhata, Fumihiko Arakawa, Takeshi Kusunoki
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Publication number: 20070091122Abstract: An information device includes a main processing circuit for executing signal processing related to a main function in the information device, a main microcomputer for controlling the main processing circuit, a receiver circuit for interfacing with the outside of the information device, and an interface microcomputer for controlling the receiver circuit, the interface microcomputer being provided separately from the main microcomputer.Type: ApplicationFiled: October 23, 2006Publication date: April 26, 2007Applicant: Renesas Technology CorporationInventors: Hideo Nagano, Kikuo Muramatsu, Masayuki Koyama, Tomoko Ando, Motoki Higashida, Takahiko Arakawa, Makoto Hatakenaka
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Publication number: 20070094627Abstract: Regions G1 to G8 each including a predetermined number of flip-flops (FF) are divided into two groups. This dividing is performed so that the number of data connection channels intersected by a boundary is minimized. In the case of intersection of two data connection channels (A1, A2), the number of data connection channels intersected by the boundary is two, the minimum number. After grouping of all the regions (G1 to G4, G5 to G8), clock tree synthesis (CTS) is performed. If clock forming is performed in this way, the increase in clock skew on an actual device can be limited and on-chip variation resistance can be increased.Type: ApplicationFiled: October 23, 2006Publication date: April 26, 2007Applicant: Renesas Technology Corp.Inventor: Michio Komoda