Abstract: The present invention discloses a high voltage metal oxide semiconductor (HVMOS) device and a method for making same. The high voltage metal oxide semiconductor device comprises: a substrate; a gate structure on the substrate; a well in the substrate, the well defining a device region from top view; a first drift region in the well; a source in the well; a drain in the first drift region, the drain being separated from the gate structure by a part of the first drift region; and a P-type dopant region not covering all the device region, wherein the P-type dopant region is formed by implanting a P-type dopant for enhancing the breakdown voltage of the HVMOS device (for N-type HVMOS device) or reducing the ON resistance of the HVMOS device (for P-type HVMOS device).

Abstract: The invention provides a micro-electro-mechanical system (MEMS) module, which includes a MEMS die stacked on an electronic circuit die. The electronic circuit die includes a substrate, the substrate including at least one through-silicon via (TSV) penetrating through the substrate; and at least one electronic circuit. The electronic circuit includes a circuit region, and a signal transmission layer directly connecting the TSV. At least one wire is connected between a middle part of the MEMS die and the TSV. There is no signal communication at the interfacing location where the MEMS die is stacked on and bonded with the electronic circuit die.

Abstract: The present invention discloses a power supply circuit with power factor correction (PFC) function, and an automatic gain control circuit therefor and a control method thereof. The power supply circuit includes the automatic gain control circuit and a load driver circuit. The automatic gain control circuit converts an input voltage to a regulation voltage, and the load driver circuit generates an output current according to the regulation voltage. The automatic gain control circuit automatically adjust the regulation voltage such that the regulation voltage has a substantially fixed amplitude or fixed average value under different input voltages of different specifications, and the output current provided by the load driver circuit varies in phase with the input voltage to provide a PFC function.

Abstract: The invention provides an analog photovoltaic power circuit with auto zero calibration, which judges whether the current trend or voltage trend has the same direction as or different direction from the power trend, and adjusts an input/output power conversion accordingly, so that an input current approaches to an optimum current corresponding to a maximum power point, in which the judgments of the current trend, voltage trend and power trend is calibrated with auto-zero circuitry.

Abstract: The present invention discloses an isolated power converter circuit and a control method thereof. The isolated power converter circuit includes: a transformer circuit, a power switch circuit, an opto-coupler circuit, and a control circuit. The transformer circuit includes a first winding and a second winding. The power switch circuit is coupled to the transformer circuit to control it according to a driving signal. The opto-coupler circuit generates a feedback signal. The control circuit is coupled to the power switch circuit and the opto-coupler circuit, for generating the driving signal according to the feedback signal. The control circuit includes a distinguishing circuit for distinguishing a status of the feedback signal.

Abstract: The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device includes: a substrate, having an isolation structure for defining a device region; a drift region located in the device region, wherein from top view, the drift region includes multiple sub-regions separated from one another but are electrically connected with one another; a source and a drain in the device region; and a gate on the surface of the substrate and between the source and drain in the device region.

Abstract: The present invention discloses a junction barrier Schottky (JBS) diode and a manufacturing method thereof. The JBS diode includes: an N-type gallium nitride (GaN) substrate; an aluminum gallium nitride (AlGaN) barrier layer, which is formed on the N-type GaN substrate; a P-type gallium nitride (GaN) layer, which is formed on or above the N-type GaN substrate; an anode conductive layer, which is formed at least partially on the AlGaN barrier layer, wherein a Schottky contact is formed between part of the anode conductive layer and the AlGaN barrier layer; and a cathode conductive layer, which is formed on the N-type GaN substrate, wherein an ohmic contact is formed between the cathode conductive layer and the N-type GaN substrate, and the cathode conductive layer is not directly connected to the anode conductive layer.

Abstract: The present invention discloses a light emitting device circuit and a control method thereof. The light emitting device circuit includes: a light emitting device control circuit, for converting an input voltage to an output voltage according to a control signal, wherein the output voltage is supplied to a light emitting device circuit; a voltage supply circuit, which is coupled to the light emitting device circuit, for generating a supply voltage from the output voltage; and a remote control circuit, which is coupled to the voltage supply circuit, for receiving the supply voltage, and generating the control signal according to a remote signal.

Abstract: The present invention discloses a light emitting device control circuit and a control method thereof, for controlling a light emitting device array display. The present invention controls not only the conduction timing and duration of one or more selected light emitting devices in the light emitting device array display, but also controls the current flowing through the selected light emitting devices by a variable current source, such that in one frame of a given length, the resolution of the brightness of the light emitting devices is increased.

Abstract: The present invention discloses a light emitting device array billboard and a control method thereof. The light emitting device array billboard includes a light emitting device array circuit, plural line switch circuits, plural channel switch circuits, plural ghost image compensation switch circuits, and a control circuit. The control circuit operates the line switch circuits and the channel switch circuit to turn ON a selected light emitting device for a duty period in a lighting period, and operates the plural ghost image compensation switch circuits to electrically connect a channel node corresponding to the selected light emitting device to a ghost image compensation voltage after the lighting period. The control circuit further adjusts a channel operation signal according to a gray scale compensation signal, to turn ON the selected light emitting device for a gray scale compensation period in addition to the duty period.

Abstract: The present invention discloses a hybrid high voltage device and a manufacturing method thereof. The hybrid high voltage device is formed in a first conductive type substrate, and includes at least one lateral double diffused metal oxide semiconductor (LDMOS) device region and at least one vent device region, wherein the LDMOS device region and the vent device region are connected in a width direction and arranged in an alternating order. Besides, corresponding high voltage wells, sources, drains, body regions, and gates of the LDMOS device region and the vent device region are connected to each other respectively.

Abstract: The present invention discloses a transient voltage suppressor (TVS) circuit, and a diode device therefor and a manufacturing method thereof. The TVS circuit is for coupling to a protected circuit to limit amplitude of a transient voltage which is inputted to the protected circuit. The TVS circuit includes a suppressor device and at least a diode device. The diode device is formed in a substrate, which includes: a well formed in the substrate; a separation region formed beneath the upper surface; a anode region and a cathode region, which are formed at two sides of the separation region beneath the upper surface respectively, wherein the anode region and the cathode region are separated by the separation region; and a buried layer, which is formed in the substrate below the well with a higher impurity density and a same conductive type as the well.

Abstract: The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device is formed in a first conductive type substrate, wherein the substrate includes isolation regions defining a device region. The high voltage device includes: a drift region, located in the device region, doped with second conductive type impurities; a gate in the device region and on the surface of the substrate; and a second conductive type source and drain in the device region, at different sides of the gate respectively. From top view, the concentration of the second conductive type impurities of the drift region is distributed substantially periodically along horizontal and vertical directions.

Abstract: The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: a first conductive type substrate, a second conductive type high voltage well, a gate, a first conductive type body region, a second conductive type source, a second conductive type drain, a first conductive type body electrode, and a first conductive type floating region. The floating region is formed in the body region, which is electrically floating and is electrically isolated from the source and the gate, such that the electrostatic discharge (ESD) effect is mitigated.

Abstract: The present invention discloses a high electron mobility transistor (HEMT) and a manufacturing method thereof. The HEMT device includes: a substrate, a first gallium nitride (GaN) layer; a P-type GaN layer, a second GaN layer, a barrier layer, a gate, a source, and a drain. The first GaN layer is formed on the substrate, and has a stepped contour from a cross-section view. The P-type GaN layer is formed on an upper step surface of the stepped contour, and has a vertical sidewall. The second GaN layer is formed on the P-type GaN layer. The barrier layer is formed on the second GaN layer. two dimensional electron gas regions are formed at junctions between the barrier layer and the first and second GaN layers. The gate is formed on an outer side of the vertical sidewall.

Abstract: The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device includes: a substrate, having an isolation structure for defining a device region; a drift region located in the device region, wherein from top view, the drift region includes multiple sub-regions separated from one another but are electrically connected with one another; a source and a drain in the device region; and a gate on the surface of the substrate and between the source and drain in the device region.

Abstract: The present invention discloses a current splitter circuit for splitting a supply current to multiple light emitting device strings of a light emitting device array. The current splitter circuit includes: a minimum selector circuit coupled to the multiple light emitting device strings to generate a minimum signal which indicates a minimum voltage of the light emitting device strings; and multiple current source circuits each including a first current source end coupled to a corresponding light emitting device string, a second current source end coupled to ground, and a current source control end receiving a current control signal related to the minimum signal, so as to control currents through the corresponding light emitting device string.

Abstract: The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: a first conductive type substrate, a second conductive type high voltage well, a gate, a first conductive type body region, a second conductive type source, a second conductive type drain, a first conductive type body electrode, and a first conductive type floating region. The floating region is formed in the body region, which is electrically floating and is electrically isolated from the source and the gate, such that the electrostatic discharge (ESD) effect is mitigated.

Abstract: A charger circuit comprising: a charging path coupled between an input voltage and a battery; a power switch on the charging path; a switch control circuit controlling the power switch; a timer counting a charging period; and a low current control circuit issuing a signal to the switch control circuit to control the power switch such that a charging current is maintained to be a predetermined low current when the timer counts to a predetermined maximum charging period.

Abstract: The present invention discloses a fuse circuit for final test trimming of an integrated circuit (IC) chip. The fuse circuit includes at least one electrical fuse, at least one control switch corresponding to the electrical fuse, and a resistant device. The electrical fuse is connected with the control switch in series between a predetermined pin and a grounding pin. The control switch receives a control signal to determine whether a predetermined current flows through the corresponding electrical fuse and breaks the electrical fuse. The resistant device is coupled between a bulk terminal and a source terminal to increase a resistance of a parasitic channel, such that an electrostatic discharge (ESD) protection is enhanced, and errors of final test trimming of an IC chip are avoided.