Abstract: A technique for improving the security of a communication device may include storing a first account identifier and a second account identifier associated with the first account identifier, the second account identifier and the first account identifier being associated with the same account on the communication device. When the communication device is interacting with a reader device to conduct a transaction, the communication device may determine whether the transaction is a proximity transaction by sensing whether a wireless interrogation signal is being transmitted from the reader device, and determine which of the first account identifier and the second account identifier to provide to the reader device based on whether the transaction is a proximity transaction.

Abstract: Structures for air-gap spacers in a field-effect transistor and methods for forming air-gap spacers in a field-effect transistor. A gate structure is formed on a top surface of a semiconductor body. A dielectric spacer is formed adjacent to a vertical sidewall of the gate structure. A semiconductor layer is formed on the top surface of the semiconductor body. The semiconductor layer is arranged relative to the vertical sidewall of the gate structure such that a first section of the first dielectric spacer is located in a space between the semiconductor layer and the vertical sidewall of the gate structure. A second section of the dielectric spacer that is located above a top surface of the semiconductor layer is removed. An air-gap spacer is formed in a space from which the second section of the dielectric spacer is removed.

Abstract: An SOI semiconductor device includes a first wafer having an active semiconductor layer and a first oxide layer and a second wafer having a semiconductor substrate and a second oxide layer, the first oxide layer being bonded to the second oxide layer, and one of the first wafer and the second wafer includes a nitride layer. The nitride layer can be formed between the semiconductor substrate and the second oxide layer. A third oxide layer can be formed on the semiconductor substrate and the nitride layer is formed between the second oxide layer and the third oxide layer. The nitride layer can be formed between the active semiconductor layer and the first oxide layer. The first wafer can include a third oxide layer formed on the active semiconductor layer and the nitride layer is formed between the third oxide layer and the first oxide layer.

Abstract: Structures for a grating coupler and methods of fabricating a structure for a grating coupler. A silicide layer is formed on a patterned section of a semiconductor layer. The grating structures of a grating coupler are formed over the silicide layer and the section of the semiconductor layer.

Abstract: A device including an SOI substrate and an isolation structure positioned at least partially in a trench that extends through a buried insulation layer and into a semiconductor bulk substrate of the SOI substrate is disclosed. The isolation structure includes a first dielectric layer positioned in a lower portion of the trench, a first material layer positioned above the first dielectric layer, the first material layer having a material different from a material of the first dielectric layer, and a second dielectric layer positioned above the first material layer, the second dielectric layer having a material different from the material of the first material layer.

Abstract: One illustrative integrated circuit product disclosed herein comprises first and second spaced-apart P-active regions positioned on a buried insulation layer positioned on a base substrate, at least one first PFET transistor in the first P-active region, and a plurality of second PFET transistors in the second P-active region, wherein the first P-active region has a first length (in the gate length direction of the device) and the second P-active region has a second length that is greater than the first length and wherein the number of second PFET transistors is greater than the number of first PFET transistors. In this example, the product also includes a tensile-stressed layer of material positioned on the at least one first PFET transistor and above the first P-active region and a compressive-stressed layer of material positioned on the plurality of second PFET transistors and above the second P-active region.

Abstract: The present disclosure is directed to etching compositions that are useful for, e.g., selectively removing silicon germanium (SiGe) from a semiconductor substrate as an intermediate step in a multistep semiconductor manufacturing process.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to cavity structures under shallow trench isolation regions and methods of manufacture. The structure includes: one or more cavity structures provided in a substrate material and sealed with an epitaxial material; and a shallow trench isolation region directly above the one or more cavity structures in the substrate material.

Abstract: An integrated circuit (IC) includes an active area including at least one active fin-type field effect transistor (FinFET), and a trench isolation adjacent to the active area. At least one inactive gate is positioned over the trench isolation. A vertically extending resistor body is positioned adjacent the at least one inactive gate over the trench isolation. A lower end of the resistor is below an upper surface of the trench isolation. The resistor reduces interconnect layer thickness to improve yield, and significantly reduces resistor footprint to enable scaling.

Abstract: One or more systems, devices, methods and storage mediums are provided herein for ablation-zone simulation, visualization, planning and/or performance. At least one system, device, method and storage medium may obtain an image volume; obtain a description of a surface that includes a shape of the surface, a size of the surface, and a location of the surface in the image volume; sample the image volume on the surface or along a ray from each surface point to another point within the shape, for example, such that sampled surface-image data is or are produced; and generate a visualization of the sampled surface-image data.

Abstract: Disclosed is an illustrative bit cell that includes a first inverter circuit that includes a first input node and a first output node and a second inverter circuit that includes a second input node and a second output node, wherein the first output node is coupled to the second input node and the second output node is coupled to the first input node. The bit cell also includes a first extension field effect transistor that includes a first gate structure, a first cell-internal S/D region and a first cell boundary node S/D region, wherein first cell-internal S/D region electrically terminates within the cell boundary. The first gate structure is electrically coupled to one of the first or second input nodes and it is also shorted to the first cell-internal S/D region.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to gap fill void and connection structures and methods of manufacture. The structure includes: a gate structure comprising source and drain regions; a gate contact in direct contact and overlapping the gate structure; and source and drain contacts directly connecting to the source and drain regions, respectively.

Abstract: The present disclosure is directed to novel germanosilicate compositions and methods of producing the same. In particular, this disclosure describes an array of transformations originating from the extra-large-pore crystalline germanosilicate compositions, designated CIT-13, possessing 10- and 14-membered rings. Included among the new materials are the new phyllosilicate compositions, designated CIT-13P, new crystalline microporous germanosilicates including high silica versions of CIT-5 and CIT-13, with and without added metal oxides, and new germanosilicate compounds designated CIT-14 and CIT-15. The disclosure also describes methods of preparing these new germanosilicate compositions as well as the compositions themselves.

Abstract: There is provided herewith an apparatus, probe, and method for the combination of near-infrared spectroscopy (NIRS) and diffuse correlation spectroscopy (DCS). The apparatus, probe and method allow for the simultaneous detection of NIRS and DCS.

Abstract: A novel synthetic crystalline aluminogermanosilicate molecular sieve material, designated SSZ-114, is provided. SSZ-114 can be synthesized by treating an aluminogermanosilicate molecular sieve of CTH framework topology with water or an aqueous solution of a mineral acid under conditions sufficient to degermanate at least a portion of aluminogermanosilicate molecular sieve to form a degermanated molecular sieve and calcining the degermanated molecular sieve under conditions sufficient to convert the degermanated molecular sieve to SSZ-114. Molecular sieve SSZ-114 may be used in organic compound conversion reactions and/or sorptive processes.

Abstract: In a self-aligned fin cut process for fabricating integrated circuits, a sacrificial gate or an epitaxially-formed source/drain region is used as an etch mask in conjunction with a fin cut etch step to remove unwanted portions of the fins. The process eliminates use of a lithographically-defined etch mask to cut the fins, which enables precise and accurate alignment of the fin cut.

Abstract: A hydrocracking catalyst comprising a zeolite beta having an average domain size from 800 to 1500 nm2; a zeolite USY; a catalyst support; and at least one metal selected from the group consisting of elements from Group 6 and Groups 8 through 10 of the Periodic Table. The zeolite beta has an OD acidity of 20 to 50 ?mol/g and the catalyst support comprises an amorphous silica aluminate and a second support material when the weight percentage content of the zeolite beta is less than the weight percentage of the zeolite USY, and, when the weight percentage content of the zeolite beta is greater than the weight percentage of the zeolite USY, the zeolite beta has an OD acidity of 20 to 400 ?mol/g, the zeolite beta content is from 0.5 to 10 wt. % and the zeolite USY has an ASDI between 0.05 and 0.12 with a corresponding zeolite USY content of from 0 to 5 wt. %. A process for hydrocracking a hydrocarbonaceous feedstock using the catalyst is also described as is a method for making the hydrocracking catalyst.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a heterojunction bipolar transistor having an emitter base junction with a silicon-oxygen lattice interface and methods of manufacture. The device includes: a collector region buried in a substrate; shallow trench isolation regions, which isolate the collector region buried in the substrate; a base region on the substrate and over the collector region; an emitter region composed of a single crystalline of semiconductor material and located over with the base region; and an oxide interface at a junction of the emitter region and the base region.

Abstract: Produced water from a crude oil or natural gas production process is purified using a membrane purification system for petroleum production, agricultural, commercial and domestic uses. The produced water is pretreated to remove, at least, particulates and oil from the produced water. The minimally pretreated water is then purified in a membrane purification system, that is operated at conditions such that membrane scaling is reduced or prevented. In particular, the membrane purification system is operated to maintain the turbidity of clarified water feed to the system or intermediate aqueous streams that are cascading through the membrane purification system. Ensuring that the turbidity of the reject streams generated in the membrane system are useful in achieving long membrane operating life.