Abstract: A NAND-type flash memory device and a method of operating the same are provided. The NAND-type flash memory device includes a cell array area, which is composed of a plurality of cell blocks sharing m bit lines, and a row decoder driving the cell array area. Each of the cell blocks includes a string select line, n word lines and a ground select line which cross the m bit lines. The row decoder includes a plurality of block drivers connected to the plurality of cell blocks, respectively. Each of the block drivers includes a first group of word driver transistors, which are connected to the odd numbered word lines, respectively, and a second group of word driver transistors, which are connected to the even numbered word lines, respectively. The gate electrodes of the word driver transistors in the first group are connected to a first driver control line, and the gate electrodes of the word driver transistors in the second group are connected to a second driver control line.