Abstract: A method of manufacturing an integrated circuit device may include forming a first etch stop layer on a first face of a substrate; forming a gate structure including a gate electrode layer and first and second source/drain regions on the first etch stop layer, the first and second source/drain regions respectively being self-aligned with opposing side walls of the gate structure and lower portions of the first and second source/drain regions respectively contacting first and second place holders extending into the substrate; removing the substrate until the first etch stop layer is exposed from a second face of the substrate while the first and second place holders are exposed; forming a base dielectric layer on a rear side of the first and second place holders; and forming a rear conductive line may be electrically connected to the second source/drain region.

Abstract: A compound of Chemical Formula 1, and an organic photoelectric device, an image sensor, and/or an electronic device including the same are disclosed: In Chemical Formula 1, each substituent is the same as defined in the detailed description.

Abstract: A plasma processing apparatus includes a chamber body including a chamber, an electrostatic chuck supporting a substrate within the chamber body and including a lower electrode, a high-frequency power supply device configured to supply high-frequency power to generate plasma with gas supplied to the chamber, and a bias power supply device configured to supply pulse power for ion acceleration to the lower electrode. The bias power supply device is configured to supply a positive voltage pulse having a duty ratio of (1-D) to the lower electrode when a target duty ratio D of an acceleration period for accelerating ions in the plasma during a process cycle exceeds a threshold.

Abstract: An image sensor includes a gate electrode on a first surface of a substrate; a photoelectric conversion region in a pixel region among the plurality of pixel regions; and a deep device isolation pattern extending around the plurality of pixel region, The deep device isolation pattern includes a vertical portion with a lowermost portion; an uppermost portion; a central portion; a lower middle portion; and an upper middle portion. A ratio of a width of the uppermost portion to a width of the central portion is between 1:0.9 and 1:1.1. The deep device isolation pattern is spaced apart from the first surface of the substrate.

Abstract: A display apparatus includes a through hole panel, a mounting module including a plurality of light emitting diodes (LEDs) and disposed to oppose the through hole panel, and a plurality of supporting reinforcement parts including a first portion of one or more supporting reinforcement parts disposed in a first direction and in contact with the through hole panel, and a second portion of one or more supporting reinforcement parts disposed in a second direction and in contact with the mounting module. The first portion and the second are configured to adjust a spacing distance between the through hole panel and the mounting module.

Abstract: Embodiments provide a heterocyclic compound, a light-emitting device including the heterocyclic compound, an electronic apparatus including the light-emitting device, and an electronic equipment including the light-emitting device.

Abstract: A display device comprises a light emitting element disposed on a substrate, a first transistor controlling a driving current supplied to the light emitting element, a second transistor supplying a data voltage to a source electrode of the first transistor, and a third transistor electrically connecting a drain electrode of the first transistor to a gate electrode of the first transistor. The second transistor comprises a semiconductor region disposed in a first active layer on the substrate and a gate electrode disposed in a first gate layer on the first active layer. The first transistor comprises a semiconductor region disposed in a second active layer on the first gate layer, a gate electrode disposed in a second gate layer on the second active layer, and a bias electrode disposed in the first active layer.

Abstract: A method includes generating, by a neural network having a plurality of layers, final feature vectors of one or more frames of a plurality of frames of an input video, while sequentially processing each of the plurality of, and generating image information corresponding to the input video based on the generated final feature vectors. For each of the plurality of frames, the generating of the final feature vectors comprises determining whether to proceed with or stop a corresponding sequenced operation through layers of the neural network for generating a final feature vector of a corresponding frame, and generating the final feature vector of the corresponding frame in response to the corresponding sequenced operation completing a final stage of the corresponding sequenced operation.

Abstract: Provided is an operation method of user equipment, the operation method including receiving a received signal including a frequency offset and a shared signal transmitted from a satellite, generating a plurality of correlation values, by correlating a search signal corresponding to the shared signal with the received signal, for each of a plurality of predefined reference frequencies, selecting a first detection window comprising a largest correlation value, among a plurality of detection windows including the plurality of correlation values corresponding to each of the plurality of reference frequencies, and identifying a target frequency for communicating with the satellite by searching a frequency band corresponding to a search width of the first detection window.

Abstract: A physical unclonable function (PUF) circuit is implemented using a Magnetoresistive Random Access Memory (MRAM) and generating an internal magnetic field to reduce a stray field of target cells. A random number is generated in the target cell by controlling a voltage applied to the target cells.

Abstract: A memory chip includes a plurality of storage blocks respectively including a plurality of memory cells; and a logic circuit configured to control the plurality of storage blocks, wherein the logic circuit includes an input/output pad configured to input data to the plurality of storage blocks and output data to the plurality of storage blocks; wherein the logic circuit is further configured to allocate block address codes having a bit inversion relationship with each other, output a mode selection signal in response to external control, output an external address code in response to the mode selection signal indicating a first addressing mode, and output an address code having a bit inversion relationship with regard to the external address code in response to the mode selection signal indicating a second addressing mode, and select a storage block to be controlled by the access command from among the plurality of storage blocks.

Abstract: A memory device includes a memory cell array including memory cells and a page buffer circuit including page buffer units respectively connected to the memory cells through a plurality of bit lines and cache latches respectively corresponding to the page buffer units, each of the page buffer units including a main latch and a pass transistor, each connected to a corresponding sensing node, sensing nodes of at least first, second, and third page buffer units of the page buffer units connected to one another through pass transistors of the first, second, and third page buffer units, and a main latch of the first page buffer unit configured to perform a first data dump operation of transferring first data to a main latch of the second page buffer unit in a first time period of a data dump period.

Abstract: A method of manufacturing a semiconductor package includes preparing a molding structure on which connection bumps are provided, forming a release layer at least partially filling spaces between the connection bumps, where the release layer includes a silicon (Si)-based polymer, forming an adhesive layer covering the release layer and the connection bumps, separating unit packages on which the release layer and the adhesive layer are formed by cutting the molding structure, the release layer, and the adhesive layer, attaching the unit packages to a base film by the adhesive layer, where the adhesive layer faces the base film, forming a shielding material layer covering at least a portion of each of the unit packages, at least a portion of the release layer, and at least a portion the adhesive layer, and separating the unit packages covered with the shielding material layer from the release layer.

Abstract: The video signal processing method comprises the steps of: downsampling luma components of reconstructed blocks adjacent to a current block; acquiring a maximum luma value from among the downsampled luma components based on a first index; acquiring a next-highest maximum luma value from among the downsampled luma components based on a second index; acquiring a maximum average luma value based on an average value of the maximum luma value and the next-highest maximum luma value; acquiring a next-lowest minimum luma value from among the downsampled luma components based on a third index; acquiring a minimum luma value from among the downsampled luma components based on a fourth index; and acquiring a minimum average luma value based on the next-lowest minimum luma value and the minimum luma value.

Abstract: Various embodiments of the present invention relate to a device and a method for merging NAN clusters by an electronic device. The electronic device may comprise a communication circuit and a processor, wherein the processor: forms a first NAN cluster with a first external electronic device; on the basis of discovery of a second NAN cluster, updates a first cluster grade of the first NAN cluster on the basis of a second merging reference value of the second NAN cluster and a first merging reference value of the first NAN cluster; and identifies the direction of merging the first NAN cluster and the second NAN cluster on the basis of the first merging reference value, the second merging reference value, the updated first cluster grade, and/or a second cluster grade of the second NAN cluster. Other embodiments may also be possible.

Abstract: A semiconductor device includes a first well region in a substrate and doped with impurities of a first conductivity type, a second well region in the substrate and doped with impurities of a second conductivity type, where the second well region is on internal sides of the first well region in a first direction that is parallel to an upper surface of the substrate, a first impurity region in the first well region and doped with impurities of the first conductivity type, a plurality of active regions in the second well region along the first direction and doped with impurities of the first conductivity type, a gate structure between the plurality of active regions in the first direction, a first dummy gate structure on the first impurity region and at least partially surrounding the second well region, and a plurality of wiring patterns.

Abstract: A display device includes a first electrode and a second electrode spaced apart from each other and disposed on a substrate; a first sub-bank disposed on the first electrode and exposing an end of the first electrode facing the second electrode; a second sub-bank disposed on the second electrode and exposing an end of the second electrode facing the first electrode; a step pattern disposed on the second electrode and overlapping at least the end of the second electrode; and a light-emitting element disposed between the first sub-bank and the second sub-bank.

Abstract: A method of manufacturing a reference sample includes discharging a droplet, obtaining a plurality of captured images by capturing the droplet according to a predetermined period with respect to an imaginary plane defined on a falling path of a discharged droplet, analyzing the plurality of captured images, and marking a point corresponding to the falling path of the droplet on a sample substrate based on a result of analyzing the plurality of captured images.

Abstract: A glass inspection equipment includes a first transfer rail extending in a first direction, where a glass including first sides and second sides extending in a direction intersecting the first sides reciprocates in the first direction, a rotation part on the first transfer rail to rotate the glass, an edge inspection part on the first transfer rail to inspect the first and second sides of the glass, and a surface inspection part which inspects a surface of the glass, the edge inspection part inspects the first sides when the glass with the first sides arranged parallel to the first direction is transferred under the edge inspection part, and the edge inspection part inspects the second sides when the glass transferred through the edge inspection part is rotated by the rotation part and the glass with the second sides parallel to the first direction is transferred under the edge inspection part.

Abstract: A memory device includes a DC conversion circuit that receives a first edge-triggered phase signal having first pulses each extending from a rising edge of a first phase signal of a multiphase clock to a later rising edge of a second phase signal of the multiphase clock and a second edge-triggered phase signal having second pulses each extending from a rising edge of the second phase signal to a later rising edge of the first phase signal, and outputting a first voltage corresponding to the first edge-triggered phase signal and a second voltage corresponding to the second edge-triggered phase signal, a comparator that compares the first voltage with the second voltage, control logic that generates a control code corresponding to an output value from the comparator, and a delay cell that delays the second phase signal according to the control code.