Patents Assigned to Samsung Austin Semiconductor, L.P.
  • Patent number: 9385018
    Abstract: A semiconductor manufacturing equipment comprising trace elements and method of manufacture are disclosed. The semiconductor manufacturing equipment includes one or more components, wherein at least one component is made from an alloy comprising one or more materials and one or more rare earth elements (REEs). The alloy comprises predetermined quantities of the respective REEs. The method for manufacturing a component includes forming an alloy comprising at least one material and one or more selected rare earth elements (REEs) and building the component with the alloy.
    Type: Grant
    Filed: January 7, 2013
    Date of Patent: July 5, 2016
    Assignee: Samsung Austin Semiconductor, L.P.
    Inventors: Dennis Winters, Victor Coots, Matthew Burnham, Daniel Thevis
  • Patent number: 9287162
    Abstract: A semiconductor structure is formed to include a non-conductive layer with at least one metal line, a first dielectric layer, a first stop layer, a second dielectric layer, a second stop layer, a third stop layer and a fourth stop layer. A first photoresist layer is formed over the upper stop layer to develop at least one via pattern. The structure is selectively etched to form the via pattern in the third stop layer through the fourth stop layer. The first photoresist layer is then removed. A second photoresist layer is formed over the upper stop layer to develop a plurality of trench patterns, each of the trench pattern comprising a via-trench portion in which the trench pattern is formed above the via pattern, and a trench portion that is remaining part of the trench pattern.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: March 15, 2016
    Assignees: Samsung Austin Semiconductor, L.P., Samsung Electronics Co., Ltd.
    Inventor: Keith Quoc Lao
  • Patent number: 9111998
    Abstract: A method for forming a multi-level stack having a multi-level contact is provided. The method includes forming a multi-level stack comprising a specified number, n, of conductive layers and at least n?1 insulating layers. A via formation layer is formed over the stack. A first via is etched in the via formation layer at a first edge of the stack. A first multi-level contact is formed in the first via. For a particular embodiment, a second via may be etched in the via formation layer at a second edge of the stack and a second multi-level contact may be formed in the second via.
    Type: Grant
    Filed: April 4, 2012
    Date of Patent: August 18, 2015
    Assignees: Samsung Electronics Co., Ltd, Samsung Austin Semiconductor L.P.
    Inventor: Keith Lao
  • Patent number: 8951095
    Abstract: Various embodiments of a semiconductor processing fluid delivery system and a method delivering a semiconductor processing fluid are provided. In aspect, a system for delivering a liquid for performing a process is provided that includes a first flow controller that has a first fluid input coupled to a first source of fluid and a second flow controller that has a second fluid input coupled to a second source of fluid. A controller is provided for generating an output signal to and thereby controlling discharges from the first and second flow controllers. A variable resistor is coupled between an output of the controller and an input of the second flow controller whereby the output signal of the controller and the resistance of the variable resistor may be selected to selectively control discharge of fluid from the first and second flow controllers.
    Type: Grant
    Filed: April 25, 2005
    Date of Patent: February 10, 2015
    Assignees: Samsung Austin Semiconductor, L.P., Samsung Electronics Co., Ltd.
    Inventors: Randall Lujan, Ahmed Ali, Michelle Garel, Josh Tucker
  • Patent number: 8887663
    Abstract: A system for use in fabrication of carbon nanotubes (CNTs) includes a wafer having a circuitry and a plurality of CNT seed sites. The system also includes a base assembly configured to support the wafer. The system further includes a first tube disposed over the wafer and configured to surround the CNTs that form on the seed sites. The circuitry in the wafer is configured to conduct at least one static charge. The wafer includes a top surface having a plurality of CNT seed sites, each seed site coupled to the circuitry and configured to receive one of the at least one static charge.
    Type: Grant
    Filed: September 27, 2011
    Date of Patent: November 18, 2014
    Assignees: Samsung Austin Semiconductor, L.P., Samsung Electronics Co., Ltd.
    Inventors: Robert Stebbins, Russell Olson
  • Publication number: 20140191409
    Abstract: A semiconductor structure is formed to include a non-conductive layer with at least one metal line, a first dielectric layer, a first stop layer, a second dielectric layer, a second stop layer, a third stop layer and a fourth stop layer. A first photoresist layer is formed over the upper stop layer to develop at least one via pattern. The structure is selectively etched to form the via pattern in the third stop layer through the fourth stop layer. The first photoresist layer is then removed. A second photoresist layer is formed over the upper stop layer to develop a plurality of trench patterns, each of the trench pattern comprising a via-trench portion in which the trench pattern is formed above the via pattern, and a trench portion that is remaining part of the trench pattern.
    Type: Application
    Filed: January 10, 2013
    Publication date: July 10, 2014
    Applicants: SAMSUNG AUSTIN SEMICONDUCTOR, L.P., SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Keith Quoc Lao
  • Patent number: 8586267
    Abstract: According to one embodiment, a pellicle includes first and second frame members that are selectively removable from one another. The second frame member has an annular shape similar to and is physically coupled to an outer periphery of a transparent membrane. The second frame member configured to be selectively coupled to the first frame member from a engaged position adjacent to the first frame member to a disengaged position in which the second frame member is separated from the first frame member.
    Type: Grant
    Filed: September 12, 2011
    Date of Patent: November 19, 2013
    Assignees: Samsung Austin Semiconductor, L.P., Samsung Electronics Co., Ltd.
    Inventor: Keith Lao
  • Patent number: 8580044
    Abstract: A system and method for semiconductor processing chamber includes a housing that can cover an annular gap of a pedestal well of the semiconductor processing chamber. A cleaning nozzle is removably coupled to a compressed dry air (CDA) supply. The cleaning nozzle can inject the CDA into the pedestal well while the housing can contain a byproduct dust agitated by the injected CDA. The byproduct dust is evacuated by at least one vacuum port that is removably coupled to a vacuum source.
    Type: Grant
    Filed: August 13, 2010
    Date of Patent: November 12, 2013
    Assignees: Samsung Austin Semiconductor, L.P., Samsung Electronics Co., Ltd.
    Inventors: Eric McCormick, Rolando Mendez, Bradley May
  • Publication number: 20130065160
    Abstract: According to one embodiment, a pellicle includes first and second frame members that are selectively removable from one another. The second frame member has an annular shape similar to and is physically coupled to an outer periphery of a transparent membrane. The second frame member configured to be selectively coupled to the first frame member from a engaged position adjacent to the first frame member to a disengaged position in which the second frame member is separated from the first frame member.
    Type: Application
    Filed: September 12, 2011
    Publication date: March 14, 2013
    Applicants: Samsung Electronics Co., Ltd., Samsung Austin Semiconductor, L.P.
    Inventor: Keith Lao
  • Patent number: 8383323
    Abstract: A system and method for selective imaging through dual photoresist layers. The system and method includes coating a surface of the wafer with a first resist and baking the wafer to sufficiently drive out solvents in the first resist. The first resist is exposed to a first radiation source and exposing an edge of the wafer having the first resist disposed thereon to the first radiation source. The method further includes hard baking the first resist to the wafer and coating the first resist with a second resist. The method also includes baking the wafer to sufficiently drive out solvents in the second resist and exposing the second resist to a second radiation source. The method also includes exposing select portions of the edge of the wafer having the second resist disposed thereon to the second radiation source and hard baking the second resist to the wafer.
    Type: Grant
    Filed: September 13, 2006
    Date of Patent: February 26, 2013
    Assignees: Samsung Austin Semiconductor, L.P., Samsung Electronics Co., Ltd.
    Inventors: Pedro Morrison, Kevin Soukup, David Cho, Karla Mendoza
  • Patent number: 8323411
    Abstract: Various embodiments of an apparatus for holding and processing semiconductor workpieces are provided. In one aspect, an apparatus is provided that includes a first base, a second base and three elongated members coupled to and between the first base and the second base. The three elongated members are spatially arranged so that a semiconductor workpiece may be positioned therebetween. Each of the elongated members has a first lateral edge, a second lateral edge and at least one radially inwardly projecting member. The at least one radially inwardly projecting member has a third lateral edge, a fourth lateral edge and an upper surface for receiving a portion of the semiconductor workpiece and a lower surface. The third lateral edge is displaced laterally inward from the first lateral edge and the fourth lateral edge is displaced laterally inward from the second lateral edge.
    Type: Grant
    Filed: June 6, 2005
    Date of Patent: December 4, 2012
    Assignee: Samsung Austin Semiconductor, L.P.
    Inventor: John Loo
  • Publication number: 20120189421
    Abstract: A system and method concurrently processes multiple wafers. A cassette structure includes multiple chucks and a drive spool for supporting and rotating the chucks. Each chuck holds a wafer in position while rotating. The cassette structure is loaded into a process chamber. Each chuck includes a self-locking mechanism that is activated by the centrifugal force generated from the rotation of the chuck. The self-locking mechanism centers and holds a wafer in position with respect to the chuck. A drive motor drives the drive spool, which causes the chucks to rotate. As the chucks are being rotated, a dispensing assembly delivers a processing chemical to the wafers.
    Type: Application
    Filed: January 21, 2011
    Publication date: July 26, 2012
    Applicant: Samsung Austin Semiconductor, L.P.
    Inventors: Amuldeep S. Brar, Nampyo Lee, Woosung Han
  • Patent number: 7759600
    Abstract: A system for producing plasma tubes that can withstand a wide variety of physical and environmental stressors within a plasma processing system is disclosed. Within such a plasma processing system, a plasma tube structure has a central body portion—having a fixed outer diameter. At a first end of the plasma tube structure, an outwardly extending flange may be provided. At a second end of the plasma tube, an edge portion is provided—having an outer diameter that is less than the fixed outer diameter of the central body portion. The edge portion is formed to facilitate easy and secure engagement of the plasma tube structure with a compression mechanism. The plasma tube structure is formed of material that provides sufficient structural integrity and degradation resistance.
    Type: Grant
    Filed: March 15, 2006
    Date of Patent: July 20, 2010
    Assignees: Samsung Austin Semiconductor, L.P., Samsung Electronics Co., Ltd.
    Inventors: David Heemstra, Kevin White
  • Patent number: 7636611
    Abstract: The present invention provides a versatile system for controlling chemical mechanical polishing in a semiconductor manufacturing process. The system of the present inventions utilizes an in-situ chemical mechanical polishing system, having some type of measurement or metrology function, to bulk polish a semiconductor wafer to a first target threshold. Once the first target has been reached, a fuzzy logic control function, communicatively coupled to the in-situ chemical mechanical polishing system, takes control of further polishing. Measurement data from the measurement function is processed by the fuzzy logic control function, which then adjusts additional polishing time for the polishing system to render a desired wafer topography.
    Type: Grant
    Filed: October 28, 2005
    Date of Patent: December 22, 2009
    Assignees: Samsung Austin Semiconductor, L.P., Samsung Electronics Co., Ltd.
    Inventor: Sugento Huandra
  • Patent number: 7486391
    Abstract: A method for haze control on a semiconductor reticle, the method including performing a reticle inspection of a semiconductor reticle to detect haze formation on a periodic basis, performing a wafer inspection to detect haze defects, forecasting haze formation, and cleaning the semiconductor reticle. Also included is a haze forecasting method for haze control on a semiconductor reticle, including scanning a plurality of semiconductor wafers, identifying repeating defects in the semiconductor wafers, storing the repeating defects in a database as known repeating defects, and identifying an additional repeating defect that is not a known repeating defect, the additional repeating defect caused by semiconductor reticle haze.
    Type: Grant
    Filed: September 13, 2006
    Date of Patent: February 3, 2009
    Assignees: Samsung Austin Semiconductor, L.P., Samsung Electronics Co., Ltd.
    Inventors: Xiaoming Chen, Maihan Nguyen, Osamu Arasaki, Tammy Maraquin, Daniel Sawyer, Pedro Morrison
  • Patent number: 7404757
    Abstract: An apparatus for breaking in new pad conditioning disks for use in a chemical mechanical polishing (CMP) system that polishes a semiconductor wafer by pressing the semiconductor wafer against a moving polishing pad. The apparatus comprises a break-in head that is removably attached to a drive shaft to which a polishing head that holds the semiconductor wafer is normally attached. The break-in head holds multiple pad conditioning disks and presses the plurality of pad conditioning disks against the moving polishing pad. The break-in head comprises a drive mechanism for rotating the multiple pad conditioning disks. The drive mechanism is coupled to the drive shaft and rotates the multiple pad conditioning disks by translating a rotating motion of the drive shaft into rotating motions of the multiple pad conditioning disks.
    Type: Grant
    Filed: June 22, 2004
    Date of Patent: July 29, 2008
    Assignees: Samsung Austin Semiconductor, L.P., Samsung Electronics Co., Ltd.
    Inventor: Randall J. Lujan
  • Patent number: 7371156
    Abstract: An off-line tool for breaking in pad conditioning disks used in a chemical mechanical polishing (CMP) system. The off-line tool comprises a platen having a first surface for holding a polishing pad and a motor for rotating the polishing pad. The motor is coupled to the platen via a first drive shaft. The off-line tool further comprises a mechanical drive assembly for holding a second drive shaft in a position proximate the first surface of the platen and a first break-in head removably attached to the second drive shaft. The first break-in head receives a first pad conditioning disk and the second drive shaft moves the first break-in head toward the platen, thereby pressing the first pad conditioning disk against the polishing pad on the platen.
    Type: Grant
    Filed: August 21, 2006
    Date of Patent: May 13, 2008
    Assignees: Samsung Electronics Co., Ltd., Samsung Austin Semiconductor, L.P.
    Inventor: Randall J. Lujan
  • Publication number: 20070066189
    Abstract: An off-line tool for breaking in pad conditioning disks used in a chemical mechanical polishing (CMP) system. The off-line tool comprises a platen having a first surface for -holding a polishing pad and a motor for rotating the polishing pad. The motor is coupled to the platen via a first drive shaft. The off-line tool further comprises a mechanical drive assembly for holding a second drive shaft in a position proximate the first surface of the platen and a first break-in head removably attached to the second drive shaft. The first break-in head receives a first pad conditioning disk and the second drive shaft moves the first break-in head toward the platen, thereby pressing the first pad-conditioning disk against the polishing pad on the platen.
    Type: Application
    Filed: August 21, 2006
    Publication date: March 22, 2007
    Applicants: SAMSUNG ELECTRONICS CO., LTD., SAMSUNG AUSTIN SEMICONDUCTOR, L.P.
    Inventor: Randall Lujan
  • Patent number: 7094134
    Abstract: An off-line tool for breaking in pad conditioning disks used in a chemical mechanical polishing (CMP) system. The off-line tool comprises a platen having a first surface for holding a polishing pad and a motor for rotating the polishing pad. The motor is coupled to the platen via a first drive shaft. The off-line tool further comprises a mechanical drive assembly for holding a second drive shaft in a position proximate the first surface of the platen and a first break-in head removably attached to the second drive shaft. The first break-in head receives a first pad conditioning disk and the second drive shaft moves the first break-in head toward the platen, thereby pressing the first pad conditioning disk against the polishing pad on the platen.
    Type: Grant
    Filed: June 22, 2004
    Date of Patent: August 22, 2006
    Assignees: Samsung Austin Semiconductor, L.P., Samsung Electronics Co., Ltd.
    Inventor: Randall J. Lujan
  • Publication number: 20060108069
    Abstract: A plasma processing system for etching a semiconductor wafer comprises: 1) a plasma chamber in which the semiconductor wafer may be mounted; 2) an upper ring capable of being mounted on an upper opening of the plasma chamber, wherein a central portion of the upper ring forms a hole; and 3) an electrode plate having a plurality of vias therethrough. The electrode plate is disposed in the hole in the upper ring, wherein the central portion of the upper ring further forms a shelf for supporting the electrode plate in the hole.
    Type: Application
    Filed: November 19, 2004
    Publication date: May 25, 2006
    Applicants: SAMSUNG ELECTRONICS Co., LTD., SAMSUNG AUSTIN SEMICONDUCTOR, L.P.
    Inventor: James Gernert