Abstract: An integrated circuit fuse circuit includes a plurality of fuses each connected to an output terminal, and a plurality of fuse programming circuits, a respective one of which is connected between a respective fuse and a reference voltage. Each of the fuse programming circuits includes a pair of complementary bipolar transistors and a field effect transistor. The pair of complementary bipolar transistors produce a large current through the associated fuse in response to a fuse programming signal which is applied to the field effect transistor. The fuse programming circuit may be fabricated in an integrated circuit by providing first and second spaced apart regions of second conductivity type in a well of first conductivity type, and a third region of the first conductivity type in the first region. An insulated gate is provided on the face between the first and second spaced apart regions. An insulated fuse is also provided on the face, electrically connected to the third region.

Abstract: A video index search control circuit for a cassette recorder utilizing 8 mm recording tape and performing tracking in response to four tracking signals of differing frequencies includes a tracking controller for controlling tracking in accordance with the tracking signals and a head for selectively recording and reproducing the tracking frequencies, a video signal and audio signal, an amplifier for varying amplitude of said tracking signals generated by said tracking controller to produce high amplitude tracking signals and a video index search system signal detector for sensing the high amplitude tracking signals and for producing a high voltage signal indicating the presence of the high amplitude tracking signals. A method for controlling a video index search function is also disclosed.

Abstract: An address input buffer of a semiconductor memory device comprises an address input terminal, a column address switch, a row address switch, a column address latch connected to the column address switch, a row address latch connected to the row address switch, and an input buffer connected to the address input terminal, and the common node of the column address switch and the row address switch and controlled by an input buffer control signal. Thus, layout area can be reduced by buffering the row and column address input signals with one input buffer without separating the column and row address buffers.