Abstract: A memory device, and an operating method of the memory device and a host device are provided. The method of operating a memory device includes receiving a command for requesting an Eye Open Monitor (EOM) operation performance from a host device, receiving pattern data including data and non-data from the host device, performing the EOM operation which performs an error count to correspond to the data, and does not perform the error count on the non-data, and transmitting an EOM response signal including the error count result to the host device.

Abstract: A semiconductor device includes a first impurity region on a substrate; a channel pattern protruding from an upper surface of the substrate, the channel pattern extending in a first direction substantially parallel to the upper surface of the substrate; a second impurity region on the channel pattern, the second impurity region covering an entire upper surface of the channel pattern; a gate structure on a sidewall of the channel pattern and the substrate adjacent to the channel pattern; a first contact pattern on the second impurity region; a second contact pattern that is electrically connected to the gate structure; and a spacer between the first contact pattern and the second contact pattern. The spacer completely surrounds the second contact pattern in plan view, and the first contact pattern partially surrounds the second contact pattern in plan view.

Abstract: A multi-stack semiconductor device includes: a plurality of lower transistor structures arranged on a lower stack and including a plurality of lower fin structures surrounded by a plurality of lower gate structures, respectively; a plurality of upper transistor structures arranged on an upper stack and including a plurality of upper fin structures surrounded by a plurality of upper gate structures, respectively; and at least one of a lower diffusion break structure on the lower stack and a upper diffusion break structure on the upper stack, wherein the lower diffusion break structure is formed between two adjacent lower gate structures, and isolates two lower transistor structures respectively including the two adjacent lower gate structures from each other, and the upper diffusion break structure is formed between two adjacent upper gate structures, and isolates two upper transistor structures respectively including the two adjacent upper gate structures from each other.

Abstract: A neural network apparatus includes a plurality of node buffers connected to a node lane and configured to store input node data by a predetermined bit size; a plurality of weight buffers connected to a weight lane and configured to store weights; and one or more processors configured to: generate first and second split data by splitting the input node data by the predetermined bit size, store the first and second split data in the node buffers, output the first split data to an operation circuit for a neural network operation on an index-by-index basis, shift the second split data, and output the second split data to the operation circuit on the index-by-index basis.

Abstract: An electronic device includes a plurality of loads, at least one processor, a plurality of regulators configured to adjust a voltage of power received from a power source and output the adjusted power, and a switching circuit configured to connect at least one of the plurality of regulators to at least one of the plurality of loads. The at least one processor is configured to identify a load to which power is to be supplied among the plurality of loads, select at least one regulator among the plurality of regulators connectable to the identified load, and control the switching circuit to connect the at least one selected regulator to the identified load.

Abstract: An integrated circuit includes: a power supply circuit configured to generate a supply voltage from at least one of first and second power source voltages; and a system load configured to operate by receiving the supply voltage through an output node of the power supply circuit, wherein the power supply circuit includes: a first low drop-output (LDO) regulator configured to generate, from the first power source voltage, a first load current flowing to the system load through the output node; and a second LDO regulator configured to selectively generate a second load current flowing to the system load through the output node, from the second power source voltage based on a difference between voltages of internal nodes of the first LDO regulator.

Abstract: A circuit chip including a substrate, first and second channel active regions on the substrate, and extending in a first direction, the second channel active regions spaced apart from the first channel regions in a second direction intersecting the first direction, first and second gate electrodes intersecting the second channel active regions, third and fourth gate electrodes intersecting the first channel active regions, and a contact electrode between the first, second, third, and fourth gate electrodes. The contact electrode including a stem section in a vertical direction, and first and second branch sections extending from the stem section and contacting a respective source/drain region on the first and second channel active regions, the first gate electrode and the third gate electrode overlapping in the second direction, and including edge portions having widths decreasing as the first gate electrode and the third gate electrode extend toward facing ends thereof.

Abstract: Provided is a method of identifying a touch type of a user touch input with respect to an electronic device, the method including: obtaining touch data from a touch input received from a user; determining a touch recognition model set consisting of touch recognition models to be used to identify a touch type of the touch input of the user from among a plurality of touch recognition models corresponding to a plurality of partial time periods included in a time in which the touch input is maintained; obtaining touch type probability values with respect to the touch input of the user by applying the touch data to the touch recognition models included in the touch recognition model set; and identifying a touch type of the touch input, based on the obtained touch type probability values.

Abstract: Provided is a semiconductor architecture including a wafer, a semiconductor device provided on the wafer, the semiconductor device including an epitaxial layer, an epitaxial contact provided on the epitaxial layer, a first via provided on the epitaxial contact, and metal lines provided on the first via, the metal lines being configured to route signals, an oxide layer provided on a first surface of the wafer and adjacent to the semiconductor device, and a buried power rail (BPR) configured to deliver power, at least a portion of the BPR being included inside of the wafer, wherein a portion of the BPR contacts the oxide layer.

Abstract: An electronic device includes a memory, a display and a processor configured to set at least one virtual plane in a three-dimensional (3D) virtual position based on at least a portion of at least one two-dimensional (2D) first image displayed on the display, set a 3D virtual space comprising the at least one virtual plane and the at least one 2D first image, insert a 3D object into the 3D virtual space, and generate at least one 2D second image by synthesizing the 3D object inserted into the 3D virtual space and the at least one 2D first image.

Abstract: A method for reading data in a storage device is provided. The method includes receiving a read command from a host device, wherein the read command indicates stored data in the storage device and a Logical Block Address (LBA) of the stored data; obtaining a Physical Block Number (PBN) based on the LBA and a Logical to Physical (L2P) mapping; determining whether the PBN corresponds to a volatile memory of the storage device; reading the stored data directly from the volatile memory based on the PBN corresponding to the volatile memory; incrementing a read counter associated with the PBN based on the stored data being read directly from the volatile memory; and reading the stored data from a non-volatile memory of the storage device based on the PBN not corresponding to the volatile memory.

Abstract: Provided is a semiconductor device including a a front-end-of-line (FEOL) structure and a back-end-of-line (BEOL) structure connected to the FEOL structure, wherein the FEOL structure includes at least one source/drain region and at least one gate structure, and the BEOL structure includes: a plurality of 1st fine metal lines arranged in a row with a same pitch, each of the plurality of 1st fine metal lines having a same width; and at least one 1st wide metal line formed at a side of the plurality of 1st fine metal lines, the 1st wide metal line having a width greater than the width of the 1st fine metal line, and wherein each of the plurality of 1st fine metal lines includes a material different from a material included in the 1st wide metal line

Abstract: A clothes dryer comprises a main body, a drum including an entrance provided to allow an object to be dried to be placed in the drum, the drum being installed inside the main body, a drying unit installed inside the main body to dry air passing through the drum, a first filter arranged adjacent to the entrance of the drum to filter air discharged from the drum, a second filter arranged between the first filter and the drying unit so as to filter air passing through the first filter, and a third filter provided to filter air passing through the second filter.

Abstract: Provided are soluble graphene quantum dots and light-emitting devices including the same. The soluble graphene quantum dot has an anthracenyl N-alkyl maleimide functional group at an edge thereof, thereby exhibiting improved solubility and/or improved emission characteristics.

Abstract: A material synthesis apparatus may include a synthesis device configured to perform a synthesis of a material of a target product; a communication interface configured to receive a first synthesis method of the target product, the first synthesis method being calculated by an external apparatus using a previously trained synthesis prediction model; and a processor configured to: determine first commands for synthesizing the target product based on the first synthesis method, schedule an order in which the first commands are executed, and control the synthesis device based on the scheduled order.

Abstract: A semiconductor device includes a lower structure including a substrate and a cell structure on the substrate and a plurality of interconnection layers, which are stacked on the lower structure in a first direction extending perpendicular to a top surface of the substrate. An uppermost interconnection layer of the plurality of interconnection layers includes uppermost conductive lines. Each of the uppermost conductive lines includes a lower metal compound pattern, a metal pattern, an upper metal compound pattern, and a capping pattern, which are sequentially stacked in the first direction. The lower metal compound pattern, the metal pattern, and the upper metal compound pattern include a same metallic element.

Abstract: The present disclosure relates to methods, devices, and systems for generating a signature of a message by a first device based on a secret key and a public key. The method includes generating a first parameter based on a first multiplication operation on the secret key and a first random number. The method further includes generating a first electronic signature based on the first parameter and the public key. The method further includes generating a second parameter based on the first random number, a second random number, and the message. The method further includes generating a second electronic signature based on the first parameter, the second parameter, the second random number, and the first electronic signature. The method further includes outputting, to a second device, the message, the first electronic signature, and the second electronic signature.

Abstract: A sound outputting apparatus is provided. The sound outputting apparatus includes a base; a plurality of speakers configured to output sound; and a cover coupled to the base, the cover including a plurality of guide flow paths that respectively correspond to the plurality of speaker. Each of the plurality of guide flow paths includes an outer hole opened in a direction that extends away from the base from a respective one of the plurality of speakers, and further includes a groove that extends in a direction toward a center of the base from the respective one of the plurality of speakers.

Abstract: An electronic device, including a memory; a display panel; an image sensor disposed at a lower end of the display panel; a processor operatively connected to the image sensor; and a display driver integrated circuit operatively connected to the display panel and the processor, and configured to sense that a first frame is output on the display panel and to transmit a first signal to the processor based on the first frame being output on the display panel, wherein the processor is configured to: generate the first frame having a designated pixel value based on a shoot command being received from a user, control the display panel to output the first frame, and control the image sensor to capture an image based on the first signal being received from the display driver integrated circuit, and store the captured image in the memory.

Abstract: An image sensor includes a pixel group. The pixel group includes a first color filter, first to third photodiodes below the first color filter such that the first color filter overlaps each of the first to third third photodiodes in a vertical direction, wherein the first to third photodiodes are arranged in a first direction perpendicular to the vertical direction, first to third floating diffusions configured to accumulate electric charges generated by the first to third photodiodes, respectively, a source follower transistor configured to output a first pixel signal based on the electric charges accumulated in at least one of the first to third floating diffusions, and a first metal layer configured to receive the first pixel signal from the source follower transistor, wherein the first metal layer extends in a second direction intersecting the first direction, wherein the first to third floating diffusions are arranged in the first direction.