Abstract: A semiconductor device includes a cell area including a plurality of word lines stacked on a substrate, at least one ground select line between the plurality of word lines and substrate, and a plurality of channel structures passing through the plurality of word lines and the at least one ground select line, and a peripheral circuit area including peripheral circuits controlling the cell area. The peripheral circuits input a first ground select bias voltage to the at least one ground select line during a first program time to a program word line selected from among the plurality of word lines, and input a second ground select bias voltage having a magnitude different from the first ground select bias voltage to the at least one ground select line during a second program time, the second program voltage different from the first program voltage.

Abstract: A flash memory device includes a memory cell array connected with word lines and control logic that performs threshold voltage compensation on the word lines through a data recover read operation. When a word line on which programming is performed after a selected word line is a dummy word line, the control logic performs the threshold voltage compensation on the selected word line based on a result of a data recover read operation of a word line on which programming is performed before the selected word line. When a next word line on which programming is performed after a selected word line is a dummy word line, the control logic performs threshold voltage compensation on the selected word line based on a result of performing the data recover read operation on a previous word line on which programming is performed before the selected word line.

Abstract: A memory system includes a plurality of memory devices having respective arrays of memory cells therein, a bus electrically coupled to and shared by the plurality of memory devices, and a memory controller. The memory controller, which is electrically coupled to the bus, includes a built-in self-test (BIST) circuit, which is commonly connected to the plurality of memory devices. The BIST circuit is configured to transfer a command set including a test pattern to the plurality of memory devices via the bus, and transfer a command trigger signal for driving the test pattern to the plurality of memory devices via the bus.

Abstract: A semiconductor device manufacturing method includes loading a semiconductor substrate into a chamber, the semiconductor substrate including a silicon oxide film, depositing a seed layer on the silicon oxide film by supplying a first silicon source material, supplying a purge gas on the seed layer, depositing a protective layer on the seed layer by repeating a first cycle, the first cycle including supplying a base source material layer and subsequently supplying the first silicon source material, and depositing a silicon nitride film on the protective layer by repeating a second cycle, the second cycle including supplying a second silicon source material and subsequently supplying a nitrogen source material.

Abstract: A substrate processing method includes: disposing a wafer in a wafer region of a tube; injecting an inert gas into a gap region, of the tube, between an inner side wall of the tube and the wafer disposed in the wafer region; and injecting a process gas into the wafer region of the tube, wherein a pressure of the gap region of the tube is higher than a pressure at an edge of the wafer region of the tube during the injection of the inert gas and the process gas.

Abstract: A micro-semiconductor chip wet alignment apparatus is provided. The micro-semiconductor chip wet alignment apparatus includes a semiconductor chip wet supply module configured to supply the plurality of micro-semiconductor chips and a liquid onto the transfer substrate so that the plurality of micro-semiconductor chips are flowable on the transfer substrate; and a chip alignment module including an absorber capable of relative movement along a surface of the transfer substrate and configured to absorb the liquid so that the plurality of micro-semiconductor chips are aligned in the plurality of grooves.

Abstract: Disclosed are semiconductor packages and their fabricating methods. The semiconductor package comprises a redistribution substrate, a semiconductor chip on a top surface of the redistribution substrate, and a solder terminal on a bottom surface of the redistribution substrate. The redistribution substrate includes an under-bump pattern in contact with the solder terminal, a dielectric layer on a sidewall of the under-bump pattern, an under-bump seed pattern between the dielectric layer and the sidewall of the under-bump pattern, and a redistribution pattern on the under-bump pattern. The under-bump pattern has central and edge regions. A first top surface at the edge region of the under-bump pattern is at a level higher than that of a second top surface at the central region of the under-bump pattern. An angle between the bottom surface and the sidewall of the under-bump pattern is in a range of 110° to 140°.

Abstract: An interconnection structure of an integrated circuit semiconductor device includes: a first conductive layer on a semiconductor substrate; an interlayer insulating layer on the first conductive layer and including a trench and a via hole; a via layer in the via hole, the via layer penetrating the interlayer insulating layer through a bottom of the trench to contact the first conductive layer, the via layer including a protrusion protruding to a height greater than a height of the trench; a barrier layer selectively on the bottom and sidewalls of the trench and on sidewalls of the via layer in the trench; a cap layer on a surface of the via layer; and a second conductive layer in the trench on the barrier layer. The cap layer is electrically connected to the first conductive layer through the via layer.

Abstract: The disclosure provides a method for generating relightable 3D portrait using a deep neural network and a computing device implementing the method. A possibility of obtaining, in real time and on computing devices having limited processing resources, realistically relighted 3D portraits having quality higher or at least comparable to quality achieved by prior art solutions, but without utilizing complex and costly equipment is provided.

Abstract: A method of manufacturing an integrated circuit having buried power rails includes forming a first dielectric layer on an upper surface of a first semiconductor substrate, forming a series of power rail trenches in an upper surface of the first dielectric layer, forming the buried power rails in the series of power rail trenches, forming a second dielectric layer on the upper surface of the first dielectric layer and upper surfaces of the buried power rails, forming a third dielectric layer on a donor wafer, bonding the third dielectric layer to the second dielectric layer, and forming a series of semiconductor devices, vias, and metal interconnects on or in the donor wafer. The buried power rails are encapsulated by the first dielectric layer and the second dielectric layer, and the buried power rails are below the plurality of semiconductor devices.

Abstract: A task execution method using resources includes receiving an execution request for a first task; analyzing the first task and dividing the first task into a plurality of sub-tasks; identifying a sub-task using a first neural network from among the sub-tasks and dividing the identified sub-task into a plurality of layer tasks corresponding to calculations between layers constituting the first neural network; calculating a deadline time of each of the sub-tasks; scheduling a first sub-task to be scheduled to a first resource group from among the resources; and, when a runtime of the first sub-task exceeds a deadline time of the first sub-task, scheduling a sub-task or a layer task subsequent to the first sub-task to a second resource group.

Abstract: A method of simplified successive cancellation list (SSCL) error decoding of S-polar codes includes representing an S-polar code as a perfect binary tree; providing a node v a vector ?v(l) of soft information from a parent node; computing a vector ?vl(l) of soft information for a left child of node v; providing node v with a vector ?vl(l) of hard decisions from the left child and using it with ?v(l) to create a soft information vector ?vr(l) and passing it to a right child of node v; providing node v with a vector ?vr(l) of hard decisions from its right child and using it with ?vl(l) to create a hard decision vector, ?v of hard decisions, and passing it to its parent node; updating, when v is a ith leaf of the perfect tree, two path metrics, and selecting paths obtained by expanding current paths with a lowest path metric.

Abstract: A method for controlling an electronic device is provided. The method includes identifying one or more user interface (UI) elements displayed on a screen of an electronic device, determining a characteristic(s) of one or more identified UI elements, generating a data base based on the characteristic of one or more identified UI elements, where the database comprises to predict NL utterances of one or more identified UI elements, where the NL utterances are predicted based on the at least one characteristic of one or more identified UI elements, receiving a voice input of a user of the electronic device, where the voice input comprises an utterance indicative of the at least one characteristic of one or more identified UI elements presented in the database, and automatically accessing UI element(s) of one or more UI elements in response to determining that the utterances of the received voice input from the user matches with the predicted NL utterances of one or more identified UI elements.

Abstract: According to various embodiments of the present invention, an electronic device may comprise: a housing comprising a first surface, a second surface, and a side surface surrounding the space between the first surface and the second surface; and a display provided in the space and exposed via the first surface. At least one of the first surface, the second surface, and the side surface may comprise: a metal alloy including at least one pore in the surface; a metal member occupying at least a portion of the inner space of the at least one pore; and an oxidation film which contacts the metal member and at least a portion of the metal alloy.

Abstract: Provided are an electronic device for sharpening an image and an operation method thereof. A method, performed by the electronic device, of sharpening an image includes: obtaining an image generated by a camera of the electronic device; obtaining a first sharpening kernel for enhancing sharpness of the image, wherein the first sharpening kernel is data including a plurality of weights to be applied to pixels in the image, the data being of a lower resolution than the image; determining coordinates corresponding to some weights indicating representative values of the first sharpening kernel from among the plurality of weights in the first sharpening kernel; generating a second sharpening kernel by selecting the weights corresponding to the determined coordinates; and obtaining a sharpened image by applying the second sharpening kernel to the image.

Abstract: According to various embodiments, a method of operating a network may include transmitting to a first user equipment (UE) connected to the network, at least one transmission signal for downlink traffic corresponding to the first UE based on a first direction, transmitting a plurality of synchronization signal blocks (SSBs) configured by the network, based on a plurality of directions corresponding respectively to the plurality of SSBs, and identifying a degree of overlap between each of the plurality of directions corresponding respectively to the plurality of SSBs and the first direction.

Abstract: An apparatus includes a memory configured to store images and a processor. The processor is configured to receive an input image. The processor is further configured to partition a human mask in the input image using a segmentation algorithm. The processor is also configured to generate a skin map based on identifying skin in the input image using the human mask. In addition, the processor is configured to process an output image with brightening applied using the skin map.

Abstract: An in-home relay device according to various embodiments may comprise: a housing; an antenna provided in the housing; an antenna alignment unit including a motor and/or circuitry for changing the position of the antenna so as to change the radiation direction of the antenna; a processor operatively connected to the antenna and the antenna alignment unit; and a communication unit including communication circuitry electrically connected to the processor and configured to wirelessly connect to external electronic devices, wherein the processor may be configured to: control the antenna alignment unit based on the quality of signals transmitted or received through the antenna to secure a line of sight (LOS) between the antenna and a repeater.

Abstract: The inventive concept provides a defect detection method of a semiconductor element, capable of promptly and accurately detecting a defect, and predicting a type of the defect with respect to various defects of the semiconductor element, and a semiconductor element manufacturing method including the defect detection method. The defect detection method is capable of promptly and accurately detecting the defect, and predicting the type of the defect with respect to various defects of the semiconductor element, by generating a first segmentation image and a second segmentation image; converting the first segmentation image and the second segmentation image into an image of a first color and a second color, respectively; generating a combination image; classifying the type of a defect; generating a defect detection model by using deep learning, and detecting a defect of the semiconductor element by using a defect detection process using the defect detection model.

Abstract: A server is disclosed. The disclosed server includes a communication device for performing communication with a home appliance and a terminal device, a memory for storing state information of the home appliance and operation pattern information obtained by analyzing an operation pattern of the home appliance, and a processor for, when a query for the home appliance is received from the terminal device, generating response information in response to the received query, and controlling the communication device to transmit the generated response information to the terminal device, wherein the processor extracts a keyword included in the received query, checks at least one state item corresponding to the extracted keyword, and generates response information by using information corresponding to at least one state item in the state information and the operation pattern information.