Abstract: A semiconductor device includes active fins extending in a first direction on a substrate; an isolation insulating layer covering a portion of side surfaces of the active fins; channel layers stacked vertically and spaced apart on the active fins; a gate pattern in a second direction across the active fins and the channel layers; and spacer layers across the active fins in the second direction on both sides of the gate pattern. At least one spacer layer extends downwardly along a side surface of the gate pattern such that a lower surface thereof contacts the isolation insulating layer. The lower surface of the spacer layer is higher than a level of upper surfaces of the active fins. The gate pattern has a lower surface contacting the isolation insulating layer. The lower surface of the gate pattern is lower than a level of the upper surfaces of the active fins.

Abstract: Provided are an electronic device and a method of manufacturing the same. The electronic device includes a ferroelectric crystallization layer between a substrate and a gate electrode and a crystallization prevention layer between the substrate and the ferroelectric crystallization layer. The ferroelectric crystallization layer is at least partially crystallized and includes a dielectric material having ferroelectricity or anti-ferroelectricity. Also, the crystallization prevention layer prevents crystallization in the ferroelectric crystallization layer from being spread toward the substrate.

Abstract: A semiconductor device and a data storage system including the same are provided. The semiconductor device includes a lower structure including a semiconductor substrate, a circuit element on the semiconductor substrate, a circuit interconnection structure on the semiconductor substrate, the circuit interconnection structure including a plurality of connection patterns on different levels and electrically connected to the circuit element, and a lower insulating structure covering the circuit element and the circuit interconnection structure; and an upper structure including an upper substrate in contact with an upper surface of the lower insulating structure, a stack structure on the upper substrate, the stack structure including interlayer insulating layers and gate electrodes alternately stacked in a vertical direction, and a vertical memory structure penetrating through the stack structure in the vertical direction.

Abstract: A carrier structure including semiconductor chip stack structures; and a carrier tape including a plurality of pockets respectively accommodating the semiconductor chip stack structures, wherein each of the plurality of pockets includes a bottom surface, first sidewalls in four corner regions of each of the plurality of pockets, and second sidewalls between adjacent first sidewalls, each of the first sidewalls has a first portion having a first inclination angle and a second portion on the first portion and having a second inclination angle, the second inclination angle being greater than the first inclination angle, and vertices of lower surfaces of the semiconductor chip stack structures are in contact with the first sidewalls.

Abstract: An integrated circuit includes a standard cell including a first active region extending in a first direction and having a first width, and a filler cell including a second active region of a same type as that of the first active region and being adjacent to the standard cell in the first direction, the second active region extending in the first direction and having a second width which is greater than the first width, wherein the standard cell further includes a first tapering portion of the same type as that of the first active region, the first tapering portion being arranged between the first active region and the second active region.

Abstract: Provided is an image sensor including a sensor substrate including a plurality of first pixels configured to sense first wavelength light in an infrared ray band and a plurality of second pixels configured to sense second wavelength light in a visible light band, and a color separating lens array disposed on the sensor substrate and configured to change a phase of the first wavelength light incident on the color separating lens array such that the first wavelength light is condensed to the plurality of first pixels, wherein the color separating lens array includes a plurality of light condensing regions configured to condense the first wavelength light respectively on the plurality of first pixels, and wherein an area of each of the plurality of light condensing regions is larger than an area of each of the plurality of first pixels.

Abstract: An electronic device is provided and includes an image sensor including a plurality of unit pixels including a first unit pixel and a second unit pixel, the first unit pixel including a first micro-lens, a first color filter disposed under the first micro-lens, and a first photodiode-array disposed under the first color filter and including a plurality of photodiodes arranged in a same number of columns and rows as each other, and the second unit pixel including a second micro-lens, a second color filter disposed under the second micro-lens and having a different color from that of the first color filter, and a second photodiode-array disposed under the second color filter and including a plurality of photodiodes arranged in a same number of columns and rows as each other; and a processor operatively coupled with the image sensor, wherein the processor is configured to identify a mode corresponding to an auto-focus function; if the mode is identified as a first mode, perform the auto-focus function based at l

Abstract: A solid ion conductor including a garnet-type oxide represented by LiAM1BLaCM2DZrEM3FM4GOHXI (Formula 1), a solid electrolyte including the solid ion conductor, an electrochemical device including the ion conductor, and a method of preparing the ion conductor are disclosed. In Formula 1, M1 is a monovalent cation, a divalent cation, a trivalent cation, or a combination thereof, M2 is a monovalent cation, a divalent cation, a trivalent cation, or a combination thereof, M3 is a divalent cation, a trivalent cation, a tetravalent cation, a pentavalent cation, a hexavalent cation, or a combination thereof, M4 is Ir, Ru, Mn, Sn, or a combination thereof, X is a monovalent anion, a divalent anion, a trivalent anion, or a combination thereof, and 6?A?8, 0?B<2, 2.8?C?3, 0?D?0.2, 0<E<2.0, 0<F<2.0, 0<G?0.2, 9?H?12, and 0?I?2 are satisfied.

Abstract: Provided are a dielectric, a device including the same, and a method of preparing the dielectric. The dielectric material includes a NaNbO3 ternary material including a perovskite phase with a Sm element substituted into a Na site such that the NaNbO3 ternary material has a permittivity of 600 or more at 1 kHz, and a temperature coefficient of capacitance (TCC) of about ?15% to about 15% in a range of about ?55° C. to about +200° C.

Abstract: A device with a neural network includes: a synaptic memory cell comprising a resistive memory element, which is disposed along an output line and which has either one of a first resistance value and a second resistance value, and configured to generate a column signal based on the resistive memory element and an input signal in response to the input signal being received through an input line; a reference memory cell comprising a reference memory element, which is disposed along a reference line and which has the second resistance value different from the first resistance value, and configured to generate a reference signal based on the reference memory element and the input signal; and an output circuit configured to generate an output signal for the output line from the column signal and the reference signal.

Abstract: A nonvolatile memory device includes a memory cell array in a first semiconductor layer and including a first memory cell connected to a first word line and a first bit line and a second memory cell connected to the first word line and a second bit line; a page buffer circuit in a second semiconductor layer and including a first page buffer connected to the first bit line, and a second page buffer connected to the second bit line; and a page buffer controller in the second semiconductor layer. The page buffer controller controls the first and second page buffers so that a develop timing of a first sensing node of the first page buffer is different from a develop timing of a second sensing node of the second page buffer. The first page buffer is closer to a through electrode region than the second page buffer.

Abstract: A memory device including: a memory cell array including a plurality of memory cells forming a plurality of strings in a vertical direction with a substrate; and a control logic configured to detect a not-open string (N/O string) from the plurality of strings in response to a write command and convert pieces of target data to be programmed on a plurality of target memory cells in the N/O string so that the pieces of target data have a value that limits a number of times a program voltage is applied to the plurality of target memory cells.

Abstract: A memory device including a plurality of nonvolatile memory chips each including a status output pin and a buffer chip configured to receive a plurality of internal state signals, which indicate states of the plurality of nonvolatile memory chips, from the status output pins and output an external state signal having a set period on the basis of the internal state signals indicating a particular state, wherein in a first section of the external state signal having the set period, a duty cycle of the external state signal determines depending on an identification (ID) of the nonvolatile memory chip which outputs the internal state signal indicating the particular state among the plurality of nonvolatile memory chips.

Abstract: The inventive concept provides a defect detection method of a semiconductor element, capable of promptly and accurately detecting a defect, and predicting a type of the defect with respect to various defects of the semiconductor element, and a semiconductor element manufacturing method including the defect detection method. The defect detection method is capable of promptly and accurately detecting the defect, and predicting the type of the defect with respect to various defects of the semiconductor element, by generating a first segmentation image and a second segmentation image; converting the first segmentation image and the second segmentation image into an image of a first color and a second color, respectively; generating a combination image; classifying the type of a defect; generating a defect detection model by using deep learning, and detecting a defect of the semiconductor element by using a defect detection process using the defect detection model.

Abstract: A semiconductor package includes a package substrate having a plurality of substrate pads, a first semiconductor chip stacked on the package substrate and having a plurality of first chip pads and first option pads along a first horizontal direction, a plurality of first sub-chip pads along a second horizontal direction, and a plurality of first wirings electrically connecting the first chip pads and the first sub-chip pads, a second semiconductor chip stacked on the first semiconductor chip to cover the first sub-chip pads, and having a plurality of second chip pads and second option pads along the first horizontal direction, a plurality of second sub-chip pads along the second horizontal direction, and a plurality of second wirings electrically connecting the second chip pads and the second sub-chip pads, and a plurality of connection lines electrically connecting the package substrate and the first and second semiconductor chips.

Abstract: A semiconductor device includes a conductive pattern extending in a first direction, a magnetic tunnel junction pattern on the conductive pattern, and a capacitor on the magnetic tunnel junction pattern. The magnetic tunnel junction pattern is between the conductive pattern and the capacitor, and the magnetic tunnel junction pattern connects to the capacitor, and the conductive pattern is configured to apply spin-orbit torque to the magnetic tunnel junction pattern.

Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a cross-coupled gate circuit in a three-dimensional (3D) stack including a plurality of transistors, a first gate line of a first transistor among the plurality of transistors connected to a fourth gate line of a fourth transistor among the plurality of transistors, a second gate line of a second transistor among the plurality of transistors connected to a third gate line of a third transistor among the plurality of transistors, a first conductor connecting the first gate line and the fourth gate line, a second conductor connecting the second gate line and the third gate line. The first gate line and the second gate line are arranged above the third gate line and the fourth gate line, respectively.

Abstract: A method for optimizing selection of a Standalone Non-Public Network (SNPN) by a User Equipment (UE), includes: receiving, from a Public Land Mobile Network (PLMN) or a SNPN, SNPN selection parameters associated with a PLMN subscription list corresponding to one or more Universal Subscriber Identity Modules (USIMs), wherein the SNPN selection parameters comprises a list of SNPNs, and a plurality of configuration parameters supported by the PLMN for the one or more USIMs; and selecting at least one SNPN from the list of SNPNs based on the PLMN subscription list and storing SNPN selection parameters along with a USIM being associated with the SNPN selection parameters.

Abstract: There is provided a method for neural network-based video encoding. The method includes estimating a motion vector between an input image and a reference image based on a temporal layer of the input image, transforming the motion vector into a latent representation, scaling the latent representation of the motion vector based on the temporal layer of the input image and obtaining a temporal context of the input image based on the scaled latent representation of the motion vector and the reference image.

Abstract: A method for seamless video capture during flex-state transition in a foldable device includes identifying, by one or more sensors of the foldable device, an initiation of a flex movement of the foldable device based on a plurality of frames of a video being captured by a source camera from among one or more cameras of the foldable device; extracting, based on the identifying of the initiation of the flex movement, a semantic scene from the plurality of frames to determine one or more regions of interest (ROIs) in the semantic scene; determining an optical flow for each of the one or more ROIs; determining a flex trajectory of the foldable device; determining a target camera from among the one or more cameras; determining a transition period to switch to the target camera; and switching capturing of the plurality of frames from the source camera to the target camera.