Abstract: A system to determine a position of one or more objects includes a transmitter to emit a beam of photons to sequentially illuminate regions of one or more objects; multiple cameras that are spaced-apart with each camera having an array of pixels to detect photons; and one or more processor devices that execute stored instructions to perform actions of a method, including: directing the transmitter to sequentially illuminate regions of one or more objects with the beam of photons; for each of the regions, receiving, from the cameras, an array position of each pixel that detected photons of the beam reflected or scattered by the region of the one or more objects; and, for each of the regions detected by the cameras, determining a position of the regions using the received array positions of the pixels that detected the photons of the beam reflected or scattered by that region.

Abstract: A method and system for providing a magnetic element and a magnetic memory utilizing the magnetic element are described. The magnetic element is used in a magnetic device that includes a contact electrically coupled to the magnetic element. The method and system include providing pinned, nonmagnetic spacer, and free layers. The free layer has an out-of-plane demagnetization energy and a perpendicular magnetic anisotropy corresponding to a perpendicular anisotropy energy that is less than the out-of-plane demagnetization energy. The nonmagnetic spacer layer is between the pinned and free layers. The method and system also include providing a perpendicular capping layer adjoining the free layer and the contact. The perpendicular capping layer induces at least part of the perpendicular magnetic anisotropy in the free layer. The magnetic element is configured to allow the free layer to be switched between magnetic states when a write current is passed through the magnetic element.

Abstract: The expression A-sign(A), where A is a signed binary integer represented in 2's complement form, sign(A) is equal to one when A is greater than zero, sign(A) is equal to zero when A is zero, and sign(A) is equal to negative one when A is less than zero, is calculated by bit-complementing A, bit-complementing (A-1) when A is less than zero, bit-complementing A when A is equal to zero, and bit-complementing (A+1) when A is greater than zero. Zero detect for A is provided by determining whether a first carry-out bit from (A+0) and a second carry-out bit from (A+1) have different logical values. In this manner, A-sign(A) can be calculated by a general purpose computer in a single instruction cycle.

Abstract: The expression A-sign(A), where A is a signed binary integer represented in 2's complement form, sign (A) is equal to one when A is greater than zero, sign (A) is equal to zero when A is zero, and sign (A) is equal to negative one when A is less than zero, is calculated by bit-complementingA, bit-complementing (A-1) when A is less than zero, bit-complementing A when A is equal to zero, and bit-complementing (A+1) when A is greater than zero. Zero detect for A is provided by determining whether a first carry-out bit from (A+0) and a second carry-out bit from (A+1) have different logical values. In this manner, A-sign (A) can be calculated by a general purpose computer in a single instruction cycle.

Abstract: The expression 2A+sign(A), where A is a signed binary integer represented in 2's complement form, sign(A) is equal to one when A is greater than zero, sign(A) is equal to zero when A is zero, and sign(A) is equal to negative one when A is less than zero, is calculated by bit-complementing A, bit-complementing (A+A+2) when A is less than zero, bit-complementing (A+A+1) when A is equal to zero, and bit-complementing all bits except a least significant bit of (A+A+1) when A is greater than zero. Zero detect for A is provided by determining whether a first carry-out bit from (A+A+1) and a second carry-out bit from (A+A+2) have different logical values. In this manner, 2A+sign(A) can be calculated by a general purpose computer in a single instruction cycle.

Abstract: A frame buffer including a memory array, circuitry for accessing the array, a plurality of latches each capable of storing a plurality of pixel values equivalent to a large portion of a row of pixels in the array which may be read simultaneously from the array, and circuitry for writing simultaneously to the memory cells of a row of the array the data stored in the latches whereby a row of pixels may be read and written back to the array bus in a minimum time period.

Abstract: A frame buffer designed to allow frame buffer operations which do not involve new row addresses to be accomplished without the need for a RAS cycle. The elimination of RAS cycles for address loading and similar functions substantially accelerates the operation of the frame buffer both as to functions which do not involve memory array addresses and those which do involve memory array addresses.

Abstract: A system device of a PC, XT or AT type computer having an ISA bus is provided with a dynamic 32-bit bus by packing circuits or PACs (142, 152) located on user add-on cards. Each PAC includes a state machine (200) which controls four tag registers (210, 211, 212, 213), four input data registers (220, 221, 222, 223), four output data registers (240, 241, 242, 243), and an output multiplexer (250). The four tag registers are for storing a byte-high enable signal BHEN and system address bits SA[1:0] associated with bytes, words, and doublewords presented to the PAC during bus write cycles. The four input data registers are for storing the bytes, words, and doublewords presented to the PAC during bus write cycles. These bytes, words, and doublewords are steered to appropriate bit positions in the input data registers by four steering circuits (214, 215, 216, 217), which are controlled by the platform type signal CR2B2.sub.-- 1 and by the output of a decoder decoding the outputs of the tag registers.

Abstract: A differential flash ADC includes an input follower differential input stage for receiving a differential input signal. The outputs of the differential input stage are coupled to legs of a differential resistive ladder having nodes cross-coupled to the inputs of a comparator array. Each leg of the differential resistor ladder is terminated by a current source.

Abstract: A balun, which does not use magnetic coupling and is easily integrated in MMICs, is formed of lumped parameter inductive and capacitive circuit elements. In one embodiment, a termination circuit is utilized to prevent reflections of common mode signals.

Abstract: A frame buffer including an array of memory cells for storing data indicating pixels to be displayed on the output display, row addressing decoding apparatus and column address decoding apparatus for selecting memory cells positioned in the array, apparatus for transferring a row address to the row addressing decoding apparatus upon the assertion of a row address strobe signal, apparatus for transferring a column address to the column address decoding apparatus for decoding upon the assertion of a first column address strobe signal, apparatus for latching a column address and any data necessary to complete the access during the first column address strobe signal, apparatus for accessing the particular column the address of which has been latched during the latching of a next subsequent address of a column to be accessed along with any data necessary to complete the next access during the next subsequent column address strobe signal following the first column address strobe signal.

Abstract: A frame buffer having a memory array, circuitry for accessing the array, a plurality of color value registers for storing a plurality of color values which may be written to the array, and circuitry for writing to the memory cells a data representing a single pixel, for writing simultaneously to the memory cells data representing a number of pixels equal to the number of conductors on the data bus, or for writing simultaneously to the memory cells data representing an entire row of pixels of the array.

Abstract: A frame buffer designed to be coupled to a data bus and to an output display in a computer system, the frame buffer including an array of memory cells for storing data indicating pixels to be displayed on the output display, address decoding apparatus for controlling access to the array, the address decoding apparatus including column address decoding apparatus for selecting groups of adjacent columns of the array, a plurality of apparatus for selectively writing to each of the columns of any of said groups of adjacent columns, a plurality of color value registers, latching apparatus for storing pixel data equivalent to a row of pixel data to be displayed on the output display, apparatus for writing pixel data from selected groups of adjacent columns of the array to the latching apparatus, and apparatus for connecting either selected ones of the color value registers, the latches, or the data bus to the apparatus for selectively writing to each of the columns of any of said groups of adjacent columns.

Abstract: A frame buffer including an array of memory cells, circuitry for accessing the memory cells to derive selected pixel data, and output circuitry for providing data signals at an output port, the output circuitry including circuitry for determining the precise time required for a data signal to rise and fall at the output port, such circuitry being selected to provide the minimum delay between succeeding data signals at the output port.

Abstract: A page in, burst-out FIFO buffer that stores only words in a single page and transfers the words to a DRAM utilizing a page mode transfer to increase data throughput and decrease latency offloading DRAM bandwidth.

Abstract: A current clamping circuit is provided which clamps a current signal to a predetermined reference current level. An input current signal and a reference current signal are supplied to the clamping circuit. The clamping circuit includes a current differencing device which determines the difference between the input current signal and the reference current signal. This current difference is summed with the original input current signal or a mirror thereof at a summing node to produce an output signal which is clamped at the predetermined reference current level.

Abstract: A duty cycle converter is provided for converting a pulsed input signal exhibiting a first duty cycle to a pulsed output signal exhibiting a second duty cycle. The converter includes an output pulse generator which synchronizes the leading edge of each output pulse with the leading edge of each input pulse. A first capacitor is charged to a first voltage level in response to a first input pulse. A second capacitor is switchably coupled to the first capacitor and, in response to a second input pulse, causes the voltage across the first capacitor to decrease to a second voltage level. A third capacitor is charged to the first voltage level in response to the second input pulse. A comparator determines when the voltage on the third capacitor increases to become equal to the second voltage level on the first capacitor.

Abstract: A keyboard interface controller in the nature of a state machine is placed in a stop mode or an idle mode after initialization. In stop or idle mode, all the keyboard conductors associated with the X-axis are activated, while all keyboard conductors associated with the Y-axis are sensed. Upon being awakened by an interrupt upon key closure from which the Y-axis location of the closed key is determined, the controller sequences through the steps of (a) determining the X-axis of the keyboard by activating the determined Y-axis conductor and sensing the X-axis conductors; (b) converting the crosspoint to a unique code; (c) transmitting the crosspoint code to the host; and (d) checking for either another closure or the release of the closure detected. When all keys are released, the controller returns to stop or idle mode.

Abstract: A frame buffer including a plurality of array planes of memory cells, row decoding circuitry for selecting rows of memory cells in each of the array planes to be accessed, column decoding circuitry for selecting columns of memory cells in each of the array planes to be accessed, a plurality of bitlines associated with the columns of memory cells of each array plane, each of the bitlines connecting to a column of memory cells and including a bitline sensing amplifier and a column select switch for providing access to the memory cells of that column of the array plane, a plurality of output sense amplifiers adapted to be connected to a selected number of bitlines in an array plane by closing of particular ones of the column select switches in the bitlines, first apparatus for providing output signals from the plurality of output sense amplifiers associated with each array plane to a data bus, and second apparatus for providing output signals from the plurality of output sense amplifiers associated with each arr

Abstract: A circuit for converting an input signal with an arbitrary duty cycle to an output signal with a 50 percent duty cycle. A bandpass filter removes unwanted DC and high frequency components from the input signal. A comparator compares the filtered signal to a reference voltage and provides very high gain amplification to produce an output signal having a 50 percent duty cycle. In one embodiment, two bandpass filters are used to condition the signal prior to providing it to the comparator. Each bandpass stage is comprised of a low pass filter followed by a high pass filter.