Abstract: A method and system for providing a magnetic element and a magnetic memory utilizing the magnetic element are described. The magnetic element is used in a magnetic device that includes a contact electrically coupled to the magnetic element. The method and system include providing pinned, nonmagnetic spacer, and free layers. The free layer has an out-of-plane demagnetization energy and a perpendicular magnetic anisotropy corresponding to a perpendicular anisotropy energy that is less than the out-of-plane demagnetization energy. The nonmagnetic spacer layer is between the pinned and free layers. The method and system also include providing a perpendicular capping layer adjoining the free layer and the contact. The perpendicular capping layer induces at least part of the perpendicular magnetic anisotropy in the free layer. The magnetic element is configured to allow the free layer to be switched between magnetic states when a write current is passed through the magnetic element.
Type:
Grant
Filed:
February 25, 2011
Date of Patent:
October 15, 2019
Assignee:
Samsung Semiconductor Inc.
Inventors:
Steven M. Watts, Zhitao Diao, Xueti Tang, Kiseok Moon, Mohamad Towfik Krounbi
Abstract: A frame buffer including a plurality of array planes of memory cells, row decoding circuitry for selecting rows of memory cells in each of the array planes to be accessed, column decoding circuitry for selecting columns of memory cells in each of the array planes to be accessed, a plurality of bitlines associated with the columns of memory cells of each array plane, each of the bitlines connecting to a column of memory cells and including a bitline sensing amplifier and a column select switch for providing access to the memory cells of that column of the array plane, a plurality of output sense amplifiers adapted to be connected to a selected number of bitlines in an array plane by closing of particular ones of the column select switches in the bitlines, first apparatus for providing output signals from the plurality of output sense amplifiers associated with each array plane to a data bus, and second apparatus for providing output signals from the plurality of output sense amplifiers associated with each arr
Type:
Grant
Filed:
October 29, 1993
Date of Patent:
August 15, 1995
Assignees:
Sun Microsystems, Inc., Samsung Semiconductor Inc.
Inventors:
Shuen C. Chang, Hai D. Ho, Szu C. Sun, Jawii Chen
Abstract: A programmable buffer chip and programming method therefor are provided in which program information is entered into the buffer chip during a time period appended to the end of an ordinary reset period and so disguised as an extension of the reset period. Program information determines the buffer status conditions to be monitored at buffer status pins, and includes first offset data and a second offset data. A non-zero value in the first offset data indicates an offset defining an almost-full condition to be monitored. A non-zero value in the second offset data indicates an offset defining an almost-empty condition to be monitored. A program indicator bit in the program information indicates whether the buffer half-full condition, or both the full and the empty condition will be monitored at a particulat buffer status pin. The buffer is programmed by first causing the buffer chip to enter a reset mode, and then entering the program information in a disguised reset period following the actual reset period.
Abstract: The present invention uses two pairs of cross coupled n-channel sense amplifier transistors attached between two electrically balanced halves of a bit line. Disposed between each pair of cross coupled n-channel sense amplifier transistors is only one pair of p-channel restore transistors attached between the bit line and complement bit line. Furthermore, on the bit line and complement bit line, between one pair of cross coupled n-channel sense amplifier transistors and the pair of p-channel restore transistors, are depletion type isolating transistors that further isolate halves of the bit line and complement bit line.