Abstract: A programmable output driver circuit is provided having multiple drive capabilities for optimising noise margins at different frequencies. Several signal paths are designed in parallel, each comprising a driver unit made up of a pull-down and a pull-up transistor. Some of the paths can be disabled by NAND gates slowing down the driver circuit to reduce the attendant noise at lower frequencies. Different types of parallel structures can be designed, allowing for variable rise and fall times of the output signal, as well as skewed duty cycles.

Abstract: A reference circuit for supplying current to high speed logic elements in an integrated circuit supplies less current when circuit temperature decreases while a supply voltage remains constant. The reference circuit supplies less current when the supply voltage increases while circuit temperature remains constant. A resistance with a temperature coefficient, in some embodiments a negative temperature coefficient, is used to decrease current flow in a first leg of an output mirror when temperature decreases. A feedback circuit is used to decrease current flow in the first leg of the output current mirror when the feedback circuit senses an increase in supply voltage by sensing a voltage change on a common control node of the output current mirror. The reference circuit sees many applications including supplying current to logic gates, input/output buffers, and sense amplifiers.

Abstract: Stored data elements are read from a first-in-first-out (FIFO) buffer memory in a pipelined fashion. A look-ahead fetching technique is utilized during a memory read cycle operation to advance (select) a subsequent data element in preparation for a next read command. Data read in advance is not output, however, until a subsequent read cycle corresponding to a next request for data in the buffer memory. A first data element written into the buffer memory is stored in an initial data register. Upon a first read request, the first data element is output from the initial data register. A first and a second memory array are provided for alternately storing successive ones of data elements written into the buffer memory. While a presently requested data element from the first array is being output, a memory cell in the second array, which contains the next data element to be requested, is selected and sensed, and the sensed value placed on an output line.

Abstract: A programmable buffer chip and programming method therefor are provided in which program information is entered into the buffer chip during a time period appended to the end of an ordinary reset period and so disguised as an extension of the reset period. Program information determines the buffer status conditions to be monitored at buffer status pins, and includes first offset data and a second offset data. A non-zero value in the first offset data indicates an offset defining an almost-full condition to be monitored. A non-zero value in the second offset data indicates an offset defining an almost-empty condition to be monitored. A program indicator bit in the program information indicates whether the buffer half-full condition, or both the full and the empty condition will be monitored at a particulat buffer status pin. The buffer is programmed by first causing the buffer chip to enter a reset mode, and then entering the program information in a disguised reset period following the actual reset period.

Abstract: A crystal oscillator circuit has a sleep mode of operation that reduces power consumption while maintaining oscillation to provide for a fast transition to a normal mode of operation.

Abstract: An output buffer with a controlled high logic state prevents the output voltage from increasing when the supply voltage, Vcc, increases. A fast low-to-high logic transition is achieved by using a pumping circuit to improve the low-to-high transition rate. However, when the Vcc voltage rises past a threshold value, the pumping circuit will only be enabled during a portion of the transition time. This prevents the output level from increasing beyond its nominal value. Because the output voltage is controlled, the high-to-low transition time is reduced and the ground bounce or noise generated by the output signal is minimized.

Abstract: In a noninverting Bi-CMOS gate, one or more passgates are utilized in the control path leading to a bipolar output transistor which switches the output of the Bi-CMOS gate. The control gate of one of the MOS transistors of a passgate is connected to an input signal of the Bi-CMOS gate. The control gate of the other MOS transistor is connected to the complement of the input signal. The output of the passgate is connected to the base of the bipolar output transistor. More than one such passgate connected to an input signal and its complement can be used. If multiple passgates are used, the outputs of the passgates may be tied together. This technique, utilizing the switching of the passgates with the input signals and their complements, is employed to create a family of Bi-CMOS noninverting gates such as buffers and AND gates. The propagation delay through the noninverting Bi-CMOS gates of the present invention are roughly equal to the propagation delay of a single Bi-CMOS inverter.

Abstract: A programmable interconnect device particularly suitable for field programmable ROM, field programmable gate array and field programmable microprocessor code, includes an intrinsic polycrystalline antifuse dielectric layer.

Abstract: The interconnect system of the present invention is comprised of a TiW metal barrier layer as well as a Ti metal barrier layer deposited on the silicon surface. An anisotropic etch process for the Ti/TiW/Al metal sandwich has also been developed without corrosion and metal residue. The addition of the Ti layer between the TiW layer and the silicon surface reduces the contact resistance between the metal and P.sup.+ silicon contact. This Ti layer also effectively improves the blocking of aluminum migration to the silicon surface through TiW grain boundaries. In order to realize good ohmic metal-P.sup.+ contacts, the surface concentration of the silicon should be very high. Therefore, the present invention also employs a plasma mode etch which removes about 250 .ANG. silicon since peak concentrations of P.sup.+ dopants (boron) are often found about 400 .ANG. below the silicon surface. This plasma mode etch will also remove silicon damage caused by previous etching.

Abstract: An intermediate Dc voltage generator providing low standby current. The present invention is a CMOS-based integrated circuit that generates a reference voltage level. The present invention accomplishes this task while also minimizing power consumption allowing application for portable computers or other battery-operated devices. The present invention replaces the second stage transistors of the prior art with transistors that have channel lengths greater than the channel lengths of the first stage transistors. This increases the turn on voltage of the second stage transistors. In addition, the channel width of the second stage transistors is less than the channel width of the first stage transistors further increasing turn on voltage. In this way, the second stage transistors are off, reducing the switching current and standby current contributed by the driver transistors at second stage, and providing intermediate level voltage references.

Abstract: A process to reduce M1/N+ contact resistance includes a low temperature anneal step, after the aluminum interconnect is alloyed at 400.degree. C. During the low temperature anneal step, the temperature of the furnace tube is lowered from 400.degree. C. to 250.degree. C. over a period of two hours, after which the integrated circuit is annealed under nitrogen for a further period of one hour. Alternately, the low temperature anneal is performed in an oven filled with nitrogen for a period of two hours at 250.degree. C.

Abstract: A charge pump having gate control voltages multiplexed to gates of FET driver circuits to precisely control charge injected by the charge pump to a low pass filter network. Large capacitors between the supply voltages and the respective gate control voltage derived from the particular supply voltage provide greater noise immunity which further reduces phase errors introduced by injected charge variations. The large capacitors help to hold the gate voltages constant, further controlling the injected charge.

Abstract: A start-up circuit for a bias generating circuit includes a current source for providing a small charging current, and transistors for coupling the charging current to the bias generating circuit during power up to force the bias generating circuit into a steady-current state. The start-up circuit also uncouples the current source from the bias circuit after the bias generating circuit is forced into the steady-current state to prevent the charging current from affecting the operation of the bias generating circuit.

Abstract: An improved crystal oscillator and output circuit is disclosed. The oscillator has a normal operating mode and a low-power mode. In the low-power mode, a reduced current which is sufficient to maintain oscillation is supplied to the oscillator and the output circuit is disabled. The oscillator can subsequently be returned to normal mode and the output circuit enabled. Since the oscillator is never shut completely off, the time required to resume normal mode oscillations is reduced.

Abstract: A programmable output driver circuit is provided having multiple drive capabilities for optimizing noise margins at different frequencies. Several signal paths are designed in parallel, each comprising a driver unit made up of a pull-down and a pull-up transistor. Some of the paths can be disabled by NAND gates slowing down the driver circuit to reduce the attendant noise at lower frequencies. Different types of parallel structures can be designed, allowing for variable rise and fall times of the output signal, as well as skewed duty cycles.

Abstract: A high-frequency voltage controlled oscillator includes a start-up circuit for preventing the oscillator from enering a stable state and that does not increase the fixed delays in the oscillator feedback paths. A sleep mode feature shuts down the oscillator to conserve power and capacitors are used to isolate the oscillator from high-frequency noise coupled through the power supply inputs.

Abstract: In a CMOS bandgap reference circuit, the respective collectors of two lateral parasitic NPN transistors are connected to the two nodes of a current mirror. The emitter circuit of the first parasitic NPN transistor includes a resistor, whereby the base-emitter junction current densities of the parasitic NPN transistors are maintained at a preselected ratio. A second resistor common to the emitter circuit of both parasitic NPN transistors is provided, whereby .DELTA.V.sub.BE having a positive temperature coefficient and V.sub.BE of the second parasitic NPN transistor having a negative temperature coefficient cancel one another. The temperature independent voltage across the common resistor and the base-emitter junction of the second transistor is buffered by a unity gain amplifier. The output of the unity gain amplifier is used to drive the parasitic NPN transistors and also is furnished as the reference voltage.

Abstract: A laser fuse signature circuit for testing whether a fuse link in an IC has been disconnected includes a first series circuit connecting the power and ground pins and a second series circuit, including the fuse and a plurality of diode devices, connecting an input pin to a first node in the first series circuit. Transistors included in the first series circuit are connected so that the laser fuse signature circuit does not conduct current during normal operation or leakage current testing of the IC.

Abstract: The present invention uses two pairs of cross coupled n-channel sense amplifier transistors attached between two electrically balanced halves of a bit line. Disposed between each pair of cross coupled n-channel sense amplifier transistors is only one pair of p-channel restore transistors attached between the bit line and complement bit line. Furthermore, on the bit line and complement bit line, between one pair of cross coupled n-channel sense amplifier transistors and the pair of p-channel restore transistors, are depletion type isolating transistors that further isolate halves of the bit line and complement bit line.