Abstract: A processor comprises a plurality of arithmetic units, an accumulator unit, and a reduction unit coupled between the plurality of arithmetic units and the accumulator unit. The reduction unit receives products of vector elements from the arithmetic units and a first accumulator value from the accumulator unit, and processes the products and the first accumulator value to generate a second accumulator value for delivery to the accumulator unit. The processor implements a plurality of vector multiply and reduce operations having guaranteed sequential semantics, that is, operations which guarantee that the computational result will be the same as that which would be produced using a corresponding sequence of individual instructions.

Abstract: A method includes identifying a first register with M bits and a second register with N bits. The process also includes shifting K bits, where K<=N, from the second register into the first register. The shifting operation executes a left shift operation including reading bits K . . . N?1 from the first register, writing bits K . . . N?1 into bit positions O . . . N?K?1 of the first register, reading K bits from the second register, and writing K bits from second register into bit positions N?K . . . N?1 of first register, or a right shift operation including reading bits O . . . N?K?1 from the first register, writing bits O . . . N?K?1 into bit position K . . . N?1 of the first register, reading the K bits from the second register, and writing K bits from second register into bit positions O . . . K?1 of first register.

Abstract: The present method of initial synchronization of a communication signal includes the steps of symbol boundary search, fractional frequency offset estimation, fractional frequency offset compensation, frame boundary search, integer frequency offset estimation, integer frequency offset compensation, preamble segment ID search and preamble cell ID search. The symbol boundary search includes estimating the boundary of a present data symbol by a correlation index for the present data symbol and the correlation index for the next data symbol. The frame boundary search includes identifying the preamble symbol in the symbols found in the symbol boundary search to determine the frame boundary. The integer frequency offset estimation is derived from the pilot subcarriers of the frame control header of the frame after locating the preamble symbol.

Abstract: The multi-band antenna structure includes a first antenna having a band width about a middle frequency and a second antenna spaced and electrically isolated from the antenna. Ends of the second antenna are shorted to each other and the antenna floats electrically. The first and second antennas are planar and superimposed in parallel planes. At least two layers of dielectric material of a thickness is between the two antennas. A third layer of dielectric material of a third thickness is between the two antennas.

Abstract: A method of multi-user detection in a given uplink and downlink time slot in a software-defined receiver which includes filtering and sampling a received signal; forming a block-banded matrix A of the sampled signals; and solving {circumflex over (d)}=T?1y, where T=(AHA), y=AHx. The methods of solving for the matrix T includes a) computing Cholesky factors of the matrix T by approximating using the block-banded property of the matrix T and A; b) Schur decomposition for Cholesky factors of the matrix T and approximating the lower triangular Cholesky factor matrix R using block Toeplitz property of matrix T; or c) Fourier Transformation.

Abstract: A processor having a reduction unit that sums m input operands plus an accumulator value, with the option of saturating after each addition or wrapping around the result of each addition. The reduction unit also allows the m input operands to be subtracted from the accumulator value by simply inverting the bits of the input operands and setting a carry into each of a plurality of reduction adders to one. The reduction unit can be used in conjunction with m parallel multipliers to quickly perform dot products and other vector operations with either saturating or wrap-around arithmetic.

Abstract: A scalar Kalman filter is applied for a Least-Square estimated value Hs at s. The filter has an input for receiving Hs, a filter equation and an out for the corrected estimated value Hsk for the kth variable. The filter equation is Hsk=KgainSn[k] wherein: correction Sn[k]=S+Kn(Hs?S); prediction of the correction S=KaSn[k]; Kalman filter gain Kn=P/(1+P); minimum predication MSE P=Ka2Pn[k]+Kb; minimum MSE Pn[k]=P (1?Kn); and Ka, Kgain and Kb are constants.

Abstract: A method for processing information is described. The method includes providing a phase reference, ?i, where the phase reference comprises N distinct values, expressed as ?i=?0 . . . ?N?1. A reset signal is received. The phase reference, ?0, is initialized in response to receipt of the reset signal. The phase reference values are repeatedly advanced from ?0 through ?N?1. The process then includes enabling at least one function at a predetermined phase reference value ?A, wherein ?A?{?0 . . . ?N?1}.

Abstract: An amplitude modulation receiver including an antenna for receiving a signal and an input filter connected to the antenna. A variable gain amplifier is connected to the input filter and is responsive to a gain control signal. An A/D converter is connected to the variable gain amplifier and is responsive to a sampling signal and provides a sampled digital signal. A D/A converter receives a demodulated signal and provides an analog output signal. A controller receives and demodulates the sampled digital signal from the A/D converter, generates the gain control signal for the variable gain amplifier, generates the sampling signal for the A/D converter, and provides the demodulated signal to the D/A converter. The demodulation and generation of the gain control signal and the sampling signal are performed in software.

Abstract: An analog TV receiver implementation on DSP allows mobile platforms to view analog TV broadcasting on LCD displays. The analog television receiver includes a demodulator for demodulating a received analog television signal, an analog to digital converter for digitizing the demodulated television signal and a digital signal processor for producing display signals from the digitized television signals. The digital signal processor being programmed to search for a horizontal synchronization signal in the television signal, track the horizontal synchronization signal and search for a vertical synchronization signal in the television signal. Next the processor separates a luminance and a pair of chrominance components of the television signal and demodulates the pair of chrominance components. Red, green and blue values are constructed from the demodulated chrominance components and the luminance components. Display signals are produced from the red, green and blue values.

Abstract: A processor comprises a memory, an instruction decoder coupled to the memory for decoding instructions retrieved therefrom, and a plurality of execution units for executing the decoded instructions. One or more of the instructions are in a compound instruction format in which a single instruction comprises multiple operation fields, with one or more of the operation fields each comprising at least an operation code field and a function field. The operation code field and the function field together specify a particular operation to be performed by one or more of the execution units.

Abstract: A method of determining an acquisition indicator bit AIs at a receiver in a communication system which includes receiving multiplexed acquisition indicator bits y=B×AI+n, where B is the signature matrix known at both base station and UE, AI is all the acquisition indicator bits and n represents noise. Next, an estimated value of the acquisition indicator bit AÎMMSE (s) as a function of ? j ? ? B T ? ( s , j ) × y ? ( j ) is calculated, where BT(s,.) is the s-th row vector of the transposed matrix BT for acquisition indicator bit AIs. Finally, the acquisition indicator bit AIs is set as follows: AIs=?1, if AÎMMSE(s)<R AIs=0, if R?AÎMMSE(s)<U AIs=1, if AÎMMSE(s)?U, where R and U are decision thresholds.

Abstract: An arithmetic unit for performing an arithmetic operation on at least first and second input operands, each of the input operands being separable into a first portion and a second portion, such as respective less significant and more significant portions. The arithmetic unit comprises first arithmetic circuitry, second arithmetic circuitry, selection circuitry and saturation circuitry. The first arithmetic circuitry, which may comprise a carry-propagate adder, processes the first portions of the input operands to generate at least a temporary sum and a carry output. The second arithmetic circuitry, which may comprise a dual adder and a preliminary saturation detector, processes the second portions of the input operands to generate one or more temporary sums and a number of saturation flags. The selection circuitry is configured to select one or more of the outputs of the second arithmetic circuitry based on the carry output of the first arithmetic circuitry.

Abstract: A method and apparatus for decoding a coded data stream of bits using an inner decoder, deinterleaver and an outer decoder. The outer decoder first decodes by error correction decoding for r errors per word. The decoding is terminated and a decoded word is outputted if the syndromes of the corrected word of the first decoding are all zeros. If the syndromes of the corrected word of the first decoding are not all zeros, a second decoding is performed by error decoding and erasure for the number of errors reduced by one and the number of erasures increased to two. The decoding is terminated and a decoded word is outputted if the syndromes of the corrected word of the second decoding are all zeros. If the syndromes of the corrected word of the second decoding are not all zeros, the second decoding by correcting and erasure decoding is repeated for the number of errors reduced by one and the number of erasures increased by two for each iteration of the second decoding.

Abstract: An adder circuit includes a plurality of adder stages interconnected in series, with a carry out of each of the adder stages other than a final adder stage being coupled to a carry in of a subsequent one of the adder stages. Carry, generate and propagate signals applied to respective inputs of a carry out computation element in at least a given one of the adder stages are substantially balanced in terms of a number of gate delays experienced by the signals within the adder circuit in arriving at their respective inputs of the carry out computation element. Advantageously, this provides significant reductions in both dynamic switching power and short circuit power in the adder circuit.

Abstract: A receiver for orthogonal frequency division multiplexing signals, including art A/D converter for converting receiver analog signals to a digital signal data stream, wherein the digital signal data stream includes symbols separated by guard segments. The receiver also includes an I/Q demodulator for producing a first set of complex I and Q components from the digital signal data stream and a guard segment length detector using the first set of I and Q components. It further includes an extractor for identifying and removing the guard segments of the detected length from the digital signal data stream and an FFT demodulator for demodulating the symbols of the digital signal data stream to produce second sets of complex I and Q components.

Abstract: Techniques for conserving power by controlling program execution in a convergence device comprising a battery or other power source and at least one processor. The processor is configured to perform processing operations associated with voice call communication functions and to perform processing operations associated with data communication functions, and is operative to execute critical programs and noncritical programs. The convergence device stores, for at least a given one of a plurality of noncritical programs associated with the data communication functions, an identifier of at least one alternate capacity program capable of performing substantially the same function as the given program but having a different power source capacity associated therewith.

Abstract: The present invention involves padding the bit sequence in the first interleaver. The present method adds to an end of the bit sequence a sufficient number of padding bits L to permit modulus 16 operation of the bit sequence. After performing the interleaving, L bits are removed from an end of the interleaved sequence. This allows the interleaving to be performed in 16-bit segments simultaneously.

Abstract: A receiver includes a controller which receives A/D sampled input signals and shifts the sampled digital signal to compensate for Doppler effect in the input signal prior to demodulation. The controller compensates for a Doppler increased frequency by shifting the sampled digital signal so as to skip a sample period every n samples. This may be achieved by decreasing a cycle of m samples by one sample period every n samples. The controller compensates for a Doppler decreased frequency by shifting the sampled digital signal so as to add a sample period every n samples. This may be achieved by repeating a sample every n samples to shift the sampled digital signal. The compensation is performed in software on a multi-threaded processor.

Abstract: A method of formulating and solving equations that facilitate recognition of full word saturating addition and subtraction The method includes formulating, for each basis addition statement z=x+y or subtraction statement z=x?y, data flow equations that describe properties of the program statements being analyzed; and solving the data flow equations. The properties may include: (a) the values BITS of program variables as Boolean functions of the sign bits of x, y and z; (b) the condition COND under which program statements are executed as Boolean functions of the sign bits of x, y and z; and (c) the condition REACH of which values of variables reach any given use of z when overflow/underflow/neither occurs.