Abstract: A method for interaction between a subscriber and an entity includes determining a current locus and acquiring change in status information for a subscriber. Preference information, for one or more searchable parameters selected by the subscriber, and association information, for one ore more contacts made by the subscriber, are acquired. First and second strength information is then acquired. First strength information pertains to the subscriber's affinity for the preference information and second strength information encompasses the subscriber's affinity for the association information. Responsive to the change in status information, a group of first entities is selected. First entity information about the group of first entities is then generated. The current locus information, the preference information, the association information, the first strength information, and the second strength information are correlated with the first entity information to produce correlation information.

Abstract: A digital signal processor is provided in a wireless communication device, wherein the processor comprises a vector unit, first and second registers coupled to and accessible by the vector unit; and an instruction set configured to perform matrix inversion of a matrix of channel values by coordinate rotation digital computer instructions using the vector unit and the first and second registers.

Abstract: The method selects registers by a register instruction field having x bits. A first group of registers has up to 2y registers and a second group of registers has up to 2z registers where y and z are at least one and not great than x. The method includes encoding an instruction field with x bits wherein y of the x bits designates a register of the first group and z bits of the x bits designates a register of the second group. The register of the first group designated by the y bits of the instruction field and the register of the second group designated by the z bits of the instruction field are selected.

Abstract: A processor comprises a plurality of arithmetic units, an accumulator unit, and a reduction unit coupled between the plurality of arithmetic units and the accumulator unit. The reduction unit receives products of vector elements from the arithmetic units and a first accumulator value from the accumulator unit, and processes the products and the first accumulator value to generate a second accumulator value for delivery to the accumulator unit. The processor implements a plurality of vector multiply and reduce operations having guaranteed sequential semantics, that is, operations which guarantee that the computational result will be the same as that which would be produced using a corresponding sequence of individual instructions.

Abstract: A method includes identifying a first register with M bits and a second register with N bits. The process also includes shifting K bits, where K<=N, from the second register into the first register. The shifting operation executes a left shift operation including reading bits K . . . N?1 from the first register, writing bits K . . . N?1 into bit positions O . . . N?K?1 of the first register, reading K bits from the second register, and writing K bits from second register into bit positions N?K . . . N?1 of first register, or a right shift operation including reading bits O . . . N?K?1 from the first register, writing bits O . . . N?K?1 into bit position K . . . N?1 of the first register, reading the K bits from the second register, and writing K bits from second register into bit positions O . . . K?1 of first register.

Abstract: The present method of initial synchronization of a communication signal includes the steps of symbol boundary search, fractional frequency offset estimation, fractional frequency offset compensation, frame boundary search, integer frequency offset estimation, integer frequency offset compensation, preamble segment ID search and preamble cell ID search. The symbol boundary search includes estimating the boundary of a present data symbol by a correlation index for the present data symbol and the correlation index for the next data symbol. The frame boundary search includes identifying the preamble symbol in the symbols found in the symbol boundary search to determine the frame boundary. The integer frequency offset estimation is derived from the pilot subcarriers of the frame control header of the frame after locating the preamble symbol.

Abstract: The multi-band antenna structure includes a first antenna having a band width about a middle frequency and a second antenna spaced and electrically isolated from the antenna. Ends of the second antenna are shorted to each other and the antenna floats electrically. The first and second antennas are planar and superimposed in parallel planes. At least two layers of dielectric material of a thickness is between the two antennas. A third layer of dielectric material of a third thickness is between the two antennas.

Abstract: A method of parallelizing a pipeline includes stages operable on a sequence of work items. The method includes allocating an amount of work for each work item, assigning at least one stage to each work item, partitioning the at least one stage into at least one team, partitioning the at least one team into at least one gang, and assigning the at least one team and the at least one gang to at least one processor. Processors, gangs, and teams are juxtaposed near one another to minimize communication losses.

Abstract: A method of multi-user detection in a given uplink and downlink time slot in a software-defined receiver which includes filtering and sampling a received signal; forming a block-banded matrix A of the sampled signals; and solving {circumflex over (d)}=T?1y, where T=(AHA), y=AHx. The methods of solving for the matrix T includes a) computing Cholesky factors of the matrix T by approximating using the block-banded property of the matrix T and A; b) Schur decomposition for Cholesky factors of the matrix T and approximating the lower triangular Cholesky factor matrix R using block Toeplitz property of matrix T; or c) Fourier Transformation.

Abstract: A method reads and compares first and second register values, each with a size of at least two bytes. A third register indicates a match if: (1) a byte in the first register value is equal to (or, alternatively, not equal to) a corresponding byte in the second register value, or (2) if a byte in the first register value is zero. Next, a fourth register value is set to one of the following: (1) a count of the matching byte, if the corresponding bytes in the first and second register values are equal (or, alternatively, are not equal), or (2) a number outside of a range between 0 and n?1, if the corresponding bytes in the first and second register values are not equal (or, alternatively, are equal). The value, n, is an integer equal to the number of bytes in the first and second register values.

Abstract: A processor having a reduction unit that sums m input operands plus an accumulator value, with the option of saturating after each addition or wrapping around the result of each addition. The reduction unit also allows the m input operands to be subtracted from the accumulator value by simply inverting the bits of the input operands and setting a carry into each of a plurality of reduction adders to one. The reduction unit can be used in conjunction with m parallel multipliers to quickly perform dot products and other vector operations with either saturating or wrap-around arithmetic.

Abstract: A method is described for use when a cache is accessed. Before all valid array entries are validated, a valid array entry is read when a data array entry is accessed. If the valid array entry is a first array value, access to the cache is treated as being invalid and the data array entry is reloaded. If the valid array entry is a second array value, a tag array entry is compared with an address to determine if the data array entry is valid or invalid. A valid control register contains a first control value before all valid array entries are validated and a second control value after all valid array entries are validated. After the second control value is established, reads of the valid array are disabled and the tag array entry is compared with the address to determine if a data array entry is valid or invalid.

Abstract: A scalar Kalman filter is applied for a Least-Square estimated value Hs at s. The filter has an input for receiving Hs, a filter equation and an out for the corrected estimated value Hsk for the kth variable. The filter equation is Hsk=KgainSn[k] wherein: correction Sn[k]=S+Kn(Hs?S); prediction of the correction S=KaSn[k]; Kalman filter gain Kn=P/(1+P); minimum predication MSE P=Ka2Pn[k]+Kb; minimum MSE Pn[k]=P (1?Kn); and Ka, Kgain and Kb are constants.

Abstract: A method for providing at least one sequence of values to a plurality of processors is described. In the method, a sequence generator from one or more sequence generators is associated with a memory location. The sequence generator is configured to generate the at least one sequence of values. One or more read accesses of the memory location are enabled by a processor from the plurality of processors. In response to enabling the read access, the sequence generator is executed so that it returns a first value from the sequence of values to the processor. After executing the sequence generator, the sequence generator is advanced so that the next access generates a second value from the sequence of values. The second value is sequentially subsequent to the first value.

Abstract: A method for processing information is described. The method includes providing a phase reference, ?i, where the phase reference comprises N distinct values, expressed as ?i=?0 . . . ?N?1. A reset signal is received. The phase reference, ?0, is initialized in response to receipt of the reset signal. The phase reference values are repeatedly advanced from ?0 through ?N?1. The process then includes enabling at least one function at a predetermined phase reference value ?A, wherein ?A?{?0 . . . ?N?1}.

Abstract: An amplitude modulation receiver including an antenna for receiving a signal and an input filter connected to the antenna. A variable gain amplifier is connected to the input filter and is responsive to a gain control signal. An A/D converter is connected to the variable gain amplifier and is responsive to a sampling signal and provides a sampled digital signal. A D/A converter receives a demodulated signal and provides an analog output signal. A controller receives and demodulates the sampled digital signal from the A/D converter, generates the gain control signal for the variable gain amplifier, generates the sampling signal for the A/D converter, and provides the demodulated signal to the D/A converter. The demodulation and generation of the gain control signal and the sampling signal are performed in software.

Abstract: The multi-band antenna structure includes a first antenna having a band width about a middle frequency and a second antenna spaced and electrically isolated from the antenna. Ends of the second antenna are shorted to each other and the antenna floats electrically. The first and second antennas are planar and superimposed in parallel planes. At least two layers of dielectric material of a thickness is between the two antennas. A third layer of dielectric material of a third thickness is between the two antennas.

Abstract: An analog TV receiver implementation on DSP allows mobile platforms to view analog TV broadcasting on LCD displays. The analog television receiver includes a demodulator for demodulating a received analog television signal, an analog to digital converter for digitizing the demodulated television signal and a digital signal processor for producing display signals from the digitized television signals. The digital signal processor being programmed to search for a horizontal synchronization signal in the television signal, track the horizontal synchronization signal and search for a vertical synchronization signal in the television signal. Next the processor separates a luminance and a pair of chrominance components of the television signal and demodulates the pair of chrominance components. Red, green and blue values are constructed from the demodulated chrominance components and the luminance components. Display signals are produced from the red, green and blue values.

Abstract: A processor comprises a memory, an instruction decoder coupled to the memory for decoding instructions retrieved therefrom, and a plurality of execution units for executing the decoded instructions. One or more of the instructions are in a compound instruction format in which a single instruction comprises multiple operation fields, with one or more of the operation fields each comprising at least an operation code field and a function field. The operation code field and the function field together specify a particular operation to be performed by one or more of the execution units.

Abstract: A method of demapping in a receiver including deriving M intermediate soft bit values yj for each of the I and Q data of the input signal as a function of the spacing in the constellation; and limiting the range of the M values yj. A look-up table index is derived for each of the limited M values yj. A look-up table, having 2N+1 entries for supporting up to N soft bit outputs, is indexed using the derived indices; and K soft bits for each of the M values yj of the I and Q data are outputted.