Abstract: A radio including a first channel for receiving signals at a first frequency and a second channel for receiving and transmitting signals at a second frequency. A multiplexer connects the first and second channels through an A/D and D/A converter to a digital signal processor. An oscillator is connected to and provides a common sampling frequency to the A/D and D/A converters. The digital signal processor controls the multiplexer and modifies the received digital signals to accommodate for the different carrier frequencies of the channels using the common sampling rate. A frequency synthesizer is connected to the oscillator and provides different frequency signals for the channels. A third channel may be provided for receiving and transmitting signals at a third frequency and is also connected to the multiplexer. The processor is capable of performing communication protocols for at least two of the channels simultaneously.

Abstract: A receiver for orthogonal frequency division multiplexing (OFDM) signals, including an A/D converter for converting received analog signals to a digital signal data stream and an OFDM demodulator for producing a first set of complex I and Q components of subcarriers from the digital signal data stream. The receiver includes a CSI estimator for estimating Channel State Information (CSI) from the sets of complex I and Q components and a TPS decoder for decoding TPS data from the sets of complex I and Q components using the CSI.

Abstract: A dipole antenna for a wireless communication device, which includes a first conductive element superimposed on a portion of and separated from a second conductive element by a first dielectric layer. A first conductive via connects the first and second conductive elements through the first dielectric layer. The second conductive element is generally U-shaped. The second conductive element includes a plurality of spaced conductive strips extending transverse from adjacent ends of the legs of the U-shape. Each strip is dimensioned for a different center frequency ?0. The first conductive element may be replaced by a coaxial feed directly to the second conductive element.

Abstract: An amplitude modulation receiver including an antenna for receiving a signal and an input filter connected to the antenna. A variable gain amplifier is connected to the input filter and is responsive to a gain control signal. An A/D converter is connected to the variable gain amplifier and is responsive to a sampling signal and provides a sampled digital signal. A D/A converter receives a demodulated signal and provides an analog output signal. A controller receives and demodulates the sampled digital signal from the A/D converter, generates the gain control signal for the variable gain amplifier, generates the sampling signal for the A/D converter, and provides the demodulated signal to the D/A converter. The demodulation and generation of the gain control signal and the sampling signal are performed in software.

Abstract: A method of extracting data from a received signal including multi-path interference in a rake receiver. The method includes sampling and filtering the received signal; estimating a time delay ?l between paths for the filtered samples ?(?); and estimating channel complex coefficient cl for the filtered samples ?(?).

Abstract: A method of decoding using a log posterior probability ratio L(uk), which is a function of forward variable ? (.) and backward variable ? (.). The method comprises dividing the forward variable ? (.) and the backward variable ? (.) into, for example, two segments p and q, where p plus q equal the length of the code word U. The forward segments ? (.) are parallel calculated, and the backward segments ? (.) are parallel calculated. The ratio L(uk) is calculated using the parallel calculated segments of ? (.) and ? (.).

Abstract: A dipole antenna for a wireless communication device, which includes a first conductive element superimposed on a portion of and separated from a second conductive element by a first dielectric layer. A first conductive via connects the first and second conductive elements through the first dielectric layer. The second conductive element is generally U-shaped. The second conductive element includes a plurality of spaced conductive strips extending transverse from adjacent ends of the legs of the U-shape. Each strip is dimensioned for a different center frequency ?0. The first conductive element may be L-shaped, and one of the legs of the L-shape being superimposed on one of the legs of the U-shape. The first conductive via connects the other leg of the L-shape to the other leg of the U-shape.

Abstract: A method of performing interleaving or deinterleaving in a communication system having at least one interleaver at the transmitter and at least one deinterleaver at the receiver. The method includes interleaving or deinterleaving the input bit sequence xn as follows: yn=x?n, n=0, . . . , N?1, using a bridge function between ?n and n, n=0, . . . , N?1, based on a spline linear model. When the system includes a first and a second interleaving or deinterleaving, the method is performed for both. When the second interleaving or deinterleaving includes adding padding bits, the location in the interleaved or deinterleaved bit sequence of the padding bits is determined and interleaving or deinterleaving for the determined locations is skipped.

Abstract: A cache memory for use in a multithreaded processor includes a number of set-associative thread caches, with one or more of the thread caches each implementing a thread-based eviction process that reduces the amount of replacement policy storage required in the cache memory. At least a given one of the thread caches in an illustrative embodiment includes a memory array having multiple sets of memory locations, and a directory for storing tags each corresponding to at least a portion of a particular address of one of the memory locations. The directory has multiple entries each storing multiple ones of the tags, such that if there are n sets of memory locations in the memory array, there are n tags associated with each directory entry. The directory is utilized in implementing a set-associative address mapping between access requests and memory locations of the memory array.

Abstract: A multithreaded processor includes an interrupt controller for processing a cross-thread interrupt directed from a requesting thread to a destination thread. The interrupt controller in an illustrative embodiment receives a request for delivery of the cross-thread interrupt to the destination thread, determines whether the destination thread of the cross-thread interrupt is enabled for receipt of cross-thread interrupts, and utilizes a thread identifier to control delivery of the cross-thread interrupt to the destination thread if the destination thread is enabled for receipt of cross-thread interrupts. The requesting thread requests delivery of the cross-thread interrupt to the destination thread by setting a corresponding interrupt pending bit in a flag register of the multithreaded processor. The destination thread is enabled for receipt of cross-thread interrupts if a corresponding enable bit is set in an enable register of the multithreaded processor.

Abstract: A multithreaded processor includes an instruction decoder for decoding retrieved instructions to determine an instruction type for each of the retrieved instructions, an integer unit coupled to the instruction decoder for processing integer type instructions, and a vector unit coupled to the instruction decoder for processing vector type instructions. A reduction unit is preferably associated with the vector unit and receives parallel data elements processed in the vector unit. The reduction unit generates a serial output from the parallel data elements. The processor may be configured to execute at least control code, digital signal processor (DSP) code, Java code and network processing code, and is therefore well-suited for use in a convergence device. The processor is preferably configured to utilize token triggered threading in conjunction with instruction pipelining.

Abstract: A method of increasing the speed of a transmitter by storing in look-up tables, modulation, spread, over-sampled and filtered samples of modulated data bits having an I and Q. The bits I and Q are differentially modulated, and the tables are indexed based on the differential modulation.

Abstract: A method of determining an acquisition indicator bit AIs at a receiver in a communication system which includes receiving multiplexed acquisition indicator bits y=B×AI+n, where B is the signature matrix known at both base station and the receiver, AI is all the acquisition indicator bits and n represents noise. Next, an estimated value of the acquisition indicator bit AÎML(s) as a function of ? j ? ? ? ? B T ? ( s , j ) × y ? ( j ) is calculated, where BT(s,.) is the s-th row vector of the transposed matrix BT for acquisition indicator bit AIs. Finally, the acquisition indicator bit AIs is set as follows: AIs=?1, if AÎML(s)<R AIs=0, if R?AÎML(s)<U AIs=1, if AÎML(s)?U, where R and U are decision thresholds.

Abstract: Techniques for thread-based memory access by a multithreaded processor are disclosed. The multithreaded processor determines a thread identifier associated with a particular processor thread, and utilizes at least a portion of the thread identifier to select a particular portion of an associated memory to be accessed by the corresponding processor thread. In an illustrative embodiment, a first portion of the thread identifier is utilized to select one of a plurality of multiple-bank memory elements within the memory, and a second portion of the thread identifier is utilized to select one of a plurality of memory banks within the selected one of the multiple-bank memory elements. The first portion may comprise one or more most significant bits of the thread identifier, while the second portion comprises one or more least significant bits of the thread identifier. Advantageously, the invention reduces memory access times and power consumption, while preventing the stalling of any processor threads.

Abstract: A cache memory for use in a multithreaded processor includes a number of set-associative thread caches, with one or more of the thread caches each implementing an eviction process based on access request address that reduces the amount of replacement policy storage required in the cache memory. At least a given one of the thread caches in an illustrative embodiment includes a memory array having multiple sets of memory locations, and a directory for storing tags each corresponding to at least a portion of a particular address of one of the memory locations. The directory has multiple entries each storing multiple ones of the tags, such that if there are n sets of memory locations in the memory array, there are n tags associated with each directory entry. The directory is utilized in implementing a set-associative address mapping between access requests and memory locations of the memory array.

Abstract: Techniques for thread-based register file access by a multithreaded processor are disclosed. The multithreaded processor determines a thread identifier associated with a particular processor thread, and utilizes at least a portion of the thread identifier to select a particular portion of an associated register file to be accessed by the corresponding processor thread. In an illustrative embodiment, the register file is divided into even and odd portions, with a least significant bit or other portion of the thread identifier being used to select either the even or the odd portion for use by a given processor thread. The thread-based register file selection may be utilized in conjunction with token triggered threading and instruction pipelining. Advantageously, the invention reduces register file port requirements and thus processor power consumption, while maintaining desired levels of concurrency.

Abstract: Techniques for token triggered multithreading in a multithreaded processor are disclosed. An instruction issuance sequence for a plurality of threads of the multithreaded processor is controlled by associating with each of the threads at least one register which stores a value identifying a next thread to be permitted to issue one or more instructions, and utilizing the stored value to control the instruction issuance sequence. For example, each of a plurality of hardware thread units of the multithreaded processor may include a corresponding local register updatable by that hardware thread unit, with the local register for a given one of the hardware thread units storing a value identifying the next thread to be permitted to issue one or more instructions after the given hardware thread unit has issued one or more instructions. A global register arrangement may also or alternatively be used.

Abstract: An amplitude modulation receiver including an antenna for receiving a signal and an input filter connected to the antenna. A variable gain amplifier is connected to the input filter and is responsive to a gain control signal. An A/D converter is connected to the variable gain amplifier and is responsive to a sampling signal and provides a sampled digital signal. A D/A converter receives a demodulated signal and provides an analog output signal. A controller receives and demodulates the sampled digital signal from the A/D converter, generates the gain control signal for the variable gain amplifier, generates the sampling signal for the A/D converter, and provides the demodulated signal to the D/A converter. The demodulation and generation of the gain control signal and the sampling signal are performed in software.

Abstract: An improved tracking system, illustrated as a delayed lock loop. The time intervals of a communication signal are tracked by first sampling the communication signal. A standard and a sample, advanced relative to each other by i sample positions from a sample position representing an assumed arrival position ta of a time interval, are correlated over a correlating length of k samples. Also, the standard and a sample retarded relative to each other by the i sample positions from the assumed arrival time ta are also correlated over k samples. A timing error is determined from the correlations. A predication of the arrival time tp of the next interval is determined from the error. One or more of the correlation length k or the i sample position is modified based on the predicated arrival time tp. The process is repeated using any of the modified correlation length k and/or sample position i. The timing error may also be used for descrambling and despreading.

Abstract: An apparatus and method for heating materials or substances in an oven at an oven temperature below their melting and/or vaporization points to either melt and/or vaporize the substance. Substances are inserted into a substantially spherical envelope. The envelope is sealed at a preset pressure. The solid is heated in an oven at an oven temperature substantially below the melting or vaporization temperature of the substance at the preset pressure for a time sufficient to either melt or vaporize the substance.