Abstract: A method of determining an acquisition indicator bit AIs at a receiver in a communication system which includes receiving multiplexed acquisition indicator bits y=B×AI+n, where B is the signature matrix known at both base station and UE, AI is all the acquisition indicator bits and n represents noise. Next, an estimated value of the acquisition indicator bit AÎMMSE (s) as a function of ? j ? ? B T ? ( s , j ) × y ? ( j ) is calculated, where BT(s,.) is the s-th row vector of the transposed matrix BT for acquisition indicator bit AIs. Finally, the acquisition indicator bit AIs is set as follows: AIs=?1, if AÎMMSE(s)<R AIs=0, if R?AÎMMSE(s)<U AIs=1, if AÎMMSE(s)?U, where R and U are decision thresholds.

Abstract: An arithmetic unit for performing an arithmetic operation on at least first and second input operands, each of the input operands being separable into a first portion and a second portion, such as respective less significant and more significant portions. The arithmetic unit comprises first arithmetic circuitry, second arithmetic circuitry, selection circuitry and saturation circuitry. The first arithmetic circuitry, which may comprise a carry-propagate adder, processes the first portions of the input operands to generate at least a temporary sum and a carry output. The second arithmetic circuitry, which may comprise a dual adder and a preliminary saturation detector, processes the second portions of the input operands to generate one or more temporary sums and a number of saturation flags. The selection circuitry is configured to select one or more of the outputs of the second arithmetic circuitry based on the carry output of the first arithmetic circuitry.

Abstract: A method which determines by an optimizing compiler whether any variable in the given program equals to the given acyclic mathematical function f(x,y, . . . ) applied to the given variables x, y, . . . in the program. In one embodiment, the method includes expressing the bits of the value of the function f(x,y, . . . ) as a Boolean function of the bits of the inputs x, y, . . . ; expressing, for every variable v and program statement s, the value taken by v when s is executed as a Boolean function V(s,v)(x, y, . . . ) of the bits of x, y, . . . ; and expressing, for every statement s, the condition under which the statement is executed as a Boolean function C(s)(x, y, . . . ) of the bits of the inputs x, y, . . . . Finally, a determination is made using a Boolean satisfiability oracle of whether, for the given variable v and program statement s, the following Boolean expression holds: C(s)(x,y, . . . )=>V(s,v)(x,y . . . )=f(x,y, . . . ).

Abstract: A method and apparatus for decoding a coded data stream of bits using an inner decoder, deinterleaver and an outer decoder. The outer decoder first decodes by error correction decoding for r errors per word. The decoding is terminated and a decoded word is outputted if the syndromes of the corrected word of the first decoding are all zeros. If the syndromes of the corrected word of the first decoding are not all zeros, a second decoding is performed by error decoding and erasure for the number of errors reduced by one and the number of erasures increased to two. The decoding is terminated and a decoded word is outputted if the syndromes of the corrected word of the second decoding are all zeros. If the syndromes of the corrected word of the second decoding are not all zeros, the second decoding by correcting and erasure decoding is repeated for the number of errors reduced by one and the number of erasures increased by two for each iteration of the second decoding.

Abstract: An adder circuit includes a plurality of adder stages interconnected in series, with a carry out of each of the adder stages other than a final adder stage being coupled to a carry in of a subsequent one of the adder stages. Carry, generate and propagate signals applied to respective inputs of a carry out computation element in at least a given one of the adder stages are substantially balanced in terms of a number of gate delays experienced by the signals within the adder circuit in arriving at their respective inputs of the carry out computation element. Advantageously, this provides significant reductions in both dynamic switching power and short circuit power in the adder circuit.

Abstract: A receiver for orthogonal frequency division multiplexing signals, including art A/D converter for converting receiver analog signals to a digital signal data stream, wherein the digital signal data stream includes symbols separated by guard segments. The receiver also includes an I/Q demodulator for producing a first set of complex I and Q components from the digital signal data stream and a guard segment length detector using the first set of I and Q components. It further includes an extractor for identifying and removing the guard segments of the detected length from the digital signal data stream and an FFT demodulator for demodulating the symbols of the digital signal data stream to produce second sets of complex I and Q components.

Abstract: Techniques for conserving power by controlling program execution in a convergence device comprising a battery or other power source and at least one processor. The processor is configured to perform processing operations associated with voice call communication functions and to perform processing operations associated with data communication functions, and is operative to execute critical programs and noncritical programs. The convergence device stores, for at least a given one of a plurality of noncritical programs associated with the data communication functions, an identifier of at least one alternate capacity program capable of performing substantially the same function as the given program but having a different power source capacity associated therewith.

Abstract: The present invention involves padding the bit sequence in the first interleaver. The present method adds to an end of the bit sequence a sufficient number of padding bits L to permit modulus 16 operation of the bit sequence. After performing the interleaving, L bits are removed from an end of the interleaved sequence. This allows the interleaving to be performed in 16-bit segments simultaneously.

Abstract: A receiver includes a controller which receives A/D sampled input signals and shifts the sampled digital signal to compensate for Doppler effect in the input signal prior to demodulation. The controller compensates for a Doppler increased frequency by shifting the sampled digital signal so as to skip a sample period every n samples. This may be achieved by decreasing a cycle of m samples by one sample period every n samples. The controller compensates for a Doppler decreased frequency by shifting the sampled digital signal so as to add a sample period every n samples. This may be achieved by repeating a sample every n samples to shift the sampled digital signal. The compensation is performed in software on a multi-threaded processor.

Abstract: A method of formulating and solving equations that facilitate recognition of full word saturating addition and subtraction The method includes formulating, for each basis addition statement z=x+y or subtraction statement z=x?y, data flow equations that describe properties of the program statements being analyzed; and solving the data flow equations. The properties may include: (a) the values BITS of program variables as Boolean functions of the sign bits of x, y and z; (b) the condition COND under which program statements are executed as Boolean functions of the sign bits of x, y and z; and (c) the condition REACH of which values of variables reach any given use of z when overflow/underflow/neither occurs.

Abstract: A radio including a first channel for receiving signals at a first frequency and a second channel for receiving and transmitting signals at a second frequency. A multiplexer connects the first and second channels through an A/D and D/A converter to a digital signal processor. An oscillator is connected to and provides a common sampling frequency to the A/D and D/A converters. The digital signal processor controls the multiplexer and modifies the received digital signals to accommodate for the different carrier frequencies of the channels using the common sampling rate. A frequency synthesizer is connected to the oscillator and provides different frequency signals for the channels. A third channel may be provided for receiving and transmitting signals at a third frequency and is also connected to the multiplexer. The processor is capable of performing communication protocols for at least two of the channels simultaneously.

Abstract: A receiver for orthogonal frequency division multiplexing (OFDM) signals, including an A/D converter for converting received analog signals to a digital signal data stream and an OFDM demodulator for producing a first set of complex I and Q components of subcarriers from the digital signal data stream. The receiver includes a CSI estimator for estimating Channel State Information (CSI) from the sets of complex I and Q components and a TPS decoder for decoding TPS data from the sets of complex I and Q components using the CSI.

Abstract: A dipole antenna for a wireless communication device, which includes a first conductive element superimposed on a portion of and separated from a second conductive element by a first dielectric layer. A first conductive via connects the first and second conductive elements through the first dielectric layer. The second conductive element is generally U-shaped. The second conductive element includes a plurality of spaced conductive strips extending transverse from adjacent ends of the legs of the U-shape. Each strip is dimensioned for a different center frequency ?0. The first conductive element may be replaced by a coaxial feed directly to the second conductive element.

Abstract: An amplitude modulation receiver including an antenna for receiving a signal and an input filter connected to the antenna. A variable gain amplifier is connected to the input filter and is responsive to a gain control signal. An A/D converter is connected to the variable gain amplifier and is responsive to a sampling signal and provides a sampled digital signal. A D/A converter receives a demodulated signal and provides an analog output signal. A controller receives and demodulates the sampled digital signal from the A/D converter, generates the gain control signal for the variable gain amplifier, generates the sampling signal for the A/D converter, and provides the demodulated signal to the D/A converter. The demodulation and generation of the gain control signal and the sampling signal are performed in software.

Abstract: A method of extracting data from a received signal including multi-path interference in a rake receiver. The method includes sampling and filtering the received signal; estimating a time delay ?l between paths for the filtered samples ?(?); and estimating channel complex coefficient cl for the filtered samples ?(?).

Abstract: A method of decoding using a log posterior probability ratio L(uk), which is a function of forward variable ? (.) and backward variable ? (.). The method comprises dividing the forward variable ? (.) and the backward variable ? (.) into, for example, two segments p and q, where p plus q equal the length of the code word U. The forward segments ? (.) are parallel calculated, and the backward segments ? (.) are parallel calculated. The ratio L(uk) is calculated using the parallel calculated segments of ? (.) and ? (.).

Abstract: A dipole antenna for a wireless communication device, which includes a first conductive element superimposed on a portion of and separated from a second conductive element by a first dielectric layer. A first conductive via connects the first and second conductive elements through the first dielectric layer. The second conductive element is generally U-shaped. The second conductive element includes a plurality of spaced conductive strips extending transverse from adjacent ends of the legs of the U-shape. Each strip is dimensioned for a different center frequency ?0. The first conductive element may be L-shaped, and one of the legs of the L-shape being superimposed on one of the legs of the U-shape. The first conductive via connects the other leg of the L-shape to the other leg of the U-shape.

Abstract: A method of performing interleaving or deinterleaving in a communication system having at least one interleaver at the transmitter and at least one deinterleaver at the receiver. The method includes interleaving or deinterleaving the input bit sequence xn as follows: yn=x?n, n=0, . . . , N?1, using a bridge function between ?n and n, n=0, . . . , N?1, based on a spline linear model. When the system includes a first and a second interleaving or deinterleaving, the method is performed for both. When the second interleaving or deinterleaving includes adding padding bits, the location in the interleaved or deinterleaved bit sequence of the padding bits is determined and interleaving or deinterleaving for the determined locations is skipped.

Abstract: A cache memory for use in a multithreaded processor includes a number of set-associative thread caches, with one or more of the thread caches each implementing a thread-based eviction process that reduces the amount of replacement policy storage required in the cache memory. At least a given one of the thread caches in an illustrative embodiment includes a memory array having multiple sets of memory locations, and a directory for storing tags each corresponding to at least a portion of a particular address of one of the memory locations. The directory has multiple entries each storing multiple ones of the tags, such that if there are n sets of memory locations in the memory array, there are n tags associated with each directory entry. The directory is utilized in implementing a set-associative address mapping between access requests and memory locations of the memory array.

Abstract: A multithreaded processor includes an interrupt controller for processing a cross-thread interrupt directed from a requesting thread to a destination thread. The interrupt controller in an illustrative embodiment receives a request for delivery of the cross-thread interrupt to the destination thread, determines whether the destination thread of the cross-thread interrupt is enabled for receipt of cross-thread interrupts, and utilizes a thread identifier to control delivery of the cross-thread interrupt to the destination thread if the destination thread is enabled for receipt of cross-thread interrupts. The requesting thread requests delivery of the cross-thread interrupt to the destination thread by setting a corresponding interrupt pending bit in a flag register of the multithreaded processor. The destination thread is enabled for receipt of cross-thread interrupts if a corresponding enable bit is set in an enable register of the multithreaded processor.