Abstract: Provided are memory cells, such as resistive random access memory (ReRAM) cells, each cell having multiple metal oxide layers formed from different oxides, and methods of manipulating and fabricating these cells. Two metal oxides used in the same cell have different dielectric constants, such as silicon oxide and hafnium oxide. The memory cell may include electrodes having different metals. Diffusivity of these metals into interfacing metal oxide layers may be different. Specifically, the lower-k oxide may be less prone to diffusion of the metal from the interfacing electrode than the higher-k oxide. The memory cell may be formed to different stable resistive levels and then resistively switched at these levels. Each level may use a different switching power. The switching level may be selected a user after fabrication of the cell and in, some embodiments, may be changed, for example, after switching the cell at a particular level.

Abstract: Methods for improving the operation of a memory array by arranging a Metal-Insulator-Metal (MIM) structure between a word line and an adjustable resistance bit line structure are described. The MIM structure may correspond with a metal/ReRAM material/metal structure that is arranged between the word line and an intrinsic polysilicon region of the adjustable resistance bit line structure. In one example, a word line (e.g., TiN) may be arranged adjacent to a ReRAM material (e.g., HfOx) that is adjacent to a first metal (e.g., TiN) that is adjacent to the intrinsic polysilicon region. The first metal may comprise a metal, metal-nitride, or a metal-silicide. In another example, the word line may be arranged adjacent to a ReRAM material that is adjacent to a first metal (e.g., TiN) that is adjacent to a second metal different from the first metal (e.g., tungsten) that is adjacent to the intrinsic polysilicon region.

Abstract: A bit scan circuit includes N scan blocks corresponding with an N-bit string of binary data. The string is scanned using an input clock signal to count the number of bits having a predetermined binary value. Each scan block includes a single latch to transfer the corresponding bit and to indicate reset. The scan blocks are organized into groups. Each group is enabled by a corresponding token signal. The token signal for each group is asserted after each preceding scan block indicates a pass value. When enabled by its token signal, the first scan block in a group is reset by a first clock signal. A second scan block in the group is enabled for reset after the first scan block indicates the pass value. The second scan block in the group is reset by a second clock signal having pulses that precede corresponding pulses from the first clock signal.

Abstract: Methods for producing RRAM resistive switching elements having reduced forming voltage include doping to create oxygen deficiencies in the dielectric film. Oxygen deficiencies in a dielectric film promote formation of conductive pathways.

Abstract: A multiple junction thin film transistor (TFT) is disclosed. The body of the TFT may have an n+ layer residing in a p? region of the body. The TFT may have an n+ source and an n+ drain on either side of the p? region of the body. Thus, the TFT has an n+/p?/n+/p?/n+ structure in this example. The n+ layer in the p? region increases the breakdown voltage. Also, drive current is increased. The impurity concentration in the n+ layer in the p? body and/or thickness of the n+ layer in the p? body may be tuned to increase performance of the TFT. In an alternative, the body of the TFT has a p+ layer residing in an n? region of the body. The TFT may have a p+ source and a p+ drain on either side of the p? region of the body.

Abstract: A three-dimensional (3D) non-volatile memory array is provided having multiple word line layers stacked vertically with interleaving insulating layers over a vertically-oriented thin film transistor (TFT). The vertically-oriented TFT is used as a bit line selection device to couple a global bit line to a vertical bit line formed in a trench between portions of the word line and insulating layer stack. The word line layers are recessed horizontally to form recesses relative to the vertical bit line trench. The horizontal recesses provide spatial separation between memory cell areas and surfaces exposed during process steps. A memory material is formed conformally within the recesses, followed by a thin protective film. The film protects the memory material during etching to expose the vertical TFT for contact to the vertical bit line. Methods of fabricating arrays including recessed memory cell areas are provided.

Abstract: A non-volatile memory is described that includes a sense amplifier that maintains a bit line voltage and output of the sense amplifier at a substantially constant voltage during read operations. During a preset phase, an output of the sense amplifier that is coupled to a selected bit line is grounded. At least one capacitor is precharged during the preset phase. During a sense phase, the sense amplifier output is disconnected from ground while the memory array is biased for reading a selected memory cell. A resulting cell current is integrated by the at least one capacitor. The integrated cell current discharges a sense node from the precharge level to an accurate voltage level based on the resulting cell current.

Abstract: Provided are methods of fabricating memory cells such as resistive random access memory (ReRAM) cells. A method involves forming a first layer including two high-k dielectric materials such that one material has a higher dielectric constant than the other material. In some embodiments, hafnium oxide and titanium oxide form the first layer. The higher-k material may be present at a lower concentration. In some embodiments, a concentration ratio of these two high-k materials is between about 3 and 7. The first layer may be formed using atomic layer deposition. The first layer is then annealed in an oxygen-containing environment. The method may proceed with forming a second layer including a low-k dielectric material, such as silicon oxide, and forming an electrode. After forming the electrode, the memory cell is annealed in a nitrogen containing environment. The nitrogen anneal may be performed at a higher temperature than the oxygen anneal.

Abstract: Independent sense amplifier addressing provides separate column addresses to individual sense amplifier groups within a single bay during one column address cycle. A memory system determines whether the individual memory cells or bits of a column at a bay can be skipped. For each sense amplifier group having at least one memory cell (or bit) that needs to be programmed, the system determines for the first column address whether the memory cell can be skipped. If a bit or memory cell having a first column address from the sense amplifier group can be skipped, the system determines a next bit having a column address from the group that needs to be programmed. The system groups the next column address for programming during the first column address cycle. The system can program a different column address for different sense amplifier groups within the bay during a single column address cycle.

Abstract: A monolithic three-dimensional memory array is provided that includes a plurality of global bit lines disposed above a substrate, each global bit line having a long axis, a plurality of vertically-oriented bit lines disposed above the global bit lines, a plurality of word lines disposed above the global bit lines, a plurality of memory cells coupled between the vertically-oriented bit lines and the word lines, and a plurality of vertically-oriented bit line select transistors coupled between the vertically-oriented bit lines and the global bit lines, each vertically-oriented bit line select transistor comprising a width and a thickness. Vertically-oriented bit line select transistors disposed above adjacent global bit lines are offset from one another in a direction along the long axis of the global bit lines. The width of each vertically-oriented bit line select transistor is greater than the thickness of the vertically-oriented bit line select transistors.

Abstract: Methods for operating a non-volatile memory that includes a plurality of memory arrays in which each memory array of the plurality of memory arrays may independently perform a SET operation, a RESET operation, or a read operation are described. The ability to independently SET or RESET memory arrays allows a SET operation to be performed on a first set of memory cells within a first memory array at the same time as a RESET operation is performed on a second set of memory cells within a second memory array. In some cases, the first memory array may be associated with a first memory bay and the second memory array may be associated with a second memory bay. Each memory bay may include a memory array, read/write circuits, and control circuitry for determining memory cell groupings and programming memory cells within the memory array based on the memory cell groupings.

Abstract: A non-volatile data storage device comprises pairs of immediately adjacent and isolated-from-one-another local bit lines that are independently driven by respective and vertically oriented bit line selector devices. The isolation between the immediately adjacent and isolated-from-one-another local bit lines also isolates from one another respective memory cells of the non-volatile data storage device such that leakage currents cannot flow from memory cells connected to a first of the immediately adjacent and isolated-from-one-another local bit lines to memory cells connected to the second of the pair of immediately adjacent and isolated-from-one-another local bit lines. A method programming a desire one of the memory cells includes applying boosting voltages to word lines adjacent to the bit line of the desired memory cell while not applying boosting voltages to word lines adjacent to the other bit line of the pair.

Abstract: A device is disclosed including one or more field effect transistors, each field effect transistor including: an elongated drain contact line including an electrically conductive material extending along a first horizontal direction; a drain including a first conductivity type semiconductor region overlaying the drain contact line; a source including a the first conductivity type semiconductor region located above the drain; and a gate extending vertically between the drain and the source.

Abstract: Embodiments of the invention generally relate to memory devices and methods for fabricating such memory devices. In one embodiment, a method for fabricating a resistive switching memory device includes depositing a metallic layer on a lower electrode disposed on a substrate and exposing the metallic layer to an activated oxygen source while heating the substrate to an oxidizing temperature within a range from about 300° C. to about 600° C. and forming a metal oxide layer from an upper portion of the metallic layer during an oxidation process. The lower electrode contains a silicon material and the metallic layer contains hafnium or zirconium. Subsequent to the oxidation process, the method further includes heating the substrate to an annealing temperature within a range from greater than 600° C. to about 850° C. while forming a metal silicide layer from a lower portion of the metallic layer during a silicidation process.

Abstract: A three-dimensional array of memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. The memory elements can be set to a low resistance state and reset to a high resistance state during standard operation by biasing appropriate voltages on the word lines and bit lines. Prior to standard operation, the memory elements undergo a forming operation, during which current through the bit lines is limited. A forming voltage is applied to the memory elements during forming with a polarity such that a higher voltage is applied to anodes and a lower voltage to cathodes.

Abstract: The manufacturing of the non-volatile storage system includes depositing one or more layers of reversible resistance-switching material for a non-volatile storage element. Prior to operation, either during manufacturing or afterwards, a forming operation is performed. In one embodiment, the forming operation includes applying a forming voltage to the one or more layers of reversible resistance-switching material to form a first region that includes a resistor and a second region that can reversibly change resistance at a low current, the resistor is formed in response to the forming condition and is not deposited on the device. In some embodiments, programming the non-volatile storage element includes applying a programming voltage that increases in voltage over time at low current but does not exceed the final forming voltage.

Abstract: Methods are provided for use with a memory array that includes a selected memory cell coupled to a selected word line and a selected bit line, with the selected word line biased at a read voltage. The method include coupling a sense amplifier to the selected bit line, the sense amplifier including a capacitor integrator, a single-transistor amplifier and a level shifter, maintaining the selected bit line at a voltage of substantially 0V using the single-transistor amplifier and the level shifter, and integrating a selected bit line current on the capacitor integrator.

Abstract: An embodiment relates to a transistor device including a pillar of semiconductor material extending vertically from a bottom portion in contact with an electrically conductive contact line, where the electrically conductive contact line extends laterally past the pillar in a horizontal direction, a gate insulating liner layer on a lateral side of the pillar, a gate electrode on the gate insulating layer extending along the lateral side of the pillar, and a region of electrically insulating semiconductor oxide material filling a space between a bottom portion of the gate electrode and a top portion of the electrically conductive contact line.

Abstract: A monolithic three-dimensional memory array is provided that includes global bit lines disposed above a substrate, each global bit line having a long axis, vertically-oriented bit lines disposed above the global bit lines, word lines disposed above the global bit lines, memory cells coupled between the vertically-oriented bit lines and the word lines, and vertically-oriented bit line select transistors coupled between the vertically-oriented bit lines and the global bit lines. Each vertically-oriented bit line select transistor has a width, a first control terminal and a second control terminal. The word lines and the vertically-oriented bit lines have a half-pitch, and the width of the vertically-oriented bit line select transistors is between about two times the half-pitch and about three times the half-pitch. Vertical bit lines disposed above adjacent global bit lines are offset from one another in a direction along the long axis of the global bit lines.

Abstract: Methods for forming a dual gate structure for a vertical TFT are described. The dual gate structure may be formed by performing a first etching process that includes forming a first set of trenches by etching a first set of oxide pillars to a first depth and forming a second set of trenches by etching a second set of oxide pillars to a second depth higher than the first depth, forming a first set of gate structures within the first set of trenches, forming a second set of gate structures within the second set of trenches, performing a second etching process that includes forming a third set of trenches by etching the first set of gate structures from a second initial depth to a third depth and forming a fourth set of trenches by etching the second set of gate structures to a fourth depth higher than the third depth.