Abstract: Methods for reducing location-based variations in the switching characteristics of memory cells within a memory array are described. In some cases, the resistance of an embedded resistor within each memory cell may be set to reduce the overall variation in series resistances for the memory cells within a memory array. For example, embedded resistors associated with far-far bits may be set to a lower resistance than embedded resistors associated with near-near bits. An embedded resistor may comprise a layer of polysilicon within a memory cell. Selective ion implantation may be used to reduce the embedded resistor resistance for memory cells within a particular region of the memory array and to form two or more different sets of embedded resistors within the memory array.

Abstract: A method is provided for reading a memory cell of a nonvolatile memory system. The method includes generating a hard bit and N soft bits for the memory cell in a total time corresponding to a single read latency period and N+1 data transfer times.

Abstract: Embodiments of the invention include a method of forming a nonvolatile memory device that contains a resistive switching memory element with improved device switching performance and lifetime, due to the addition of a current limiting component. In one embodiment, the current limiting component comprises a resistive material configured to improve the switching performance and lifetime of the resistive switching memory element. The electrical properties of the current limiting layer are configured to lower the current flow through the variable resistance layer during the logic state programming steps by adding a fixed series resistance in the resistive switching memory element found in the nonvolatile memory device. In one embodiment, the current limiting component comprises a tunnel oxide layer that is a current limiting material and an oxygen barrier layer that is an oxygen deficient material disposed within a resistive switching memory element in a nonvolatile resistive switching memory device.

Abstract: Embodiments of the invention generally include a method of forming a nonvolatile memory device that contains a resistive switching memory element that has an improved device switching performance and lifetime, due to the addition of a current limiting component disposed therein. In one embodiment, the current limiting component comprises at least one layer of resistive material that is configured to improve the switching performance and lifetime of the formed resistive switching memory element. The electrical properties of the formed current limiting layer, or resistive layer, are configured to lower the current flow through the variable resistance layer during the logic state programming steps (i.e., “set” and “reset” steps) by adding a fixed series resistance in the formed resistive switching memory element found in the nonvolatile memory device.

Abstract: In a 3D memory with vertical local bit lines, each local bit line is switchably connected to a node on a global bit line having first and second ends, the local bit line voltage is maintained at a predetermined reference level in spite of being driven by a bit line driver from a first end of the global bit line that constitutes variable circuit path length and circuit serial resistance. This is accomplished by a feedback voltage regulator comprising a voltage clamp at the first end of the global bit line controlled by a bit line voltage comparator at the second end of the global bit line. The comparator compares the bit line voltage sensed from the second end with the predetermined reference level and outputs a control voltage to control the voltage clamp In this way the voltage at the local bit line is regulated at the reference voltage.

Abstract: Three-dimensional (3D) non-volatile memory arrays having a vertically-oriented thin film transistor (TFT) select device and methods of fabricating such a memory are described. The vertically-oriented TFT may be used as a vertical bit line selection device to couple a global bit line to a vertical bit line. A select device pillar includes a body and upper and lower source/drain regions. At least one gate is separated horizontally from the select device pillar by a gate dielectric. The gates overlie the global bit lines with one or more insulating layers therebetween to provide adequate isolation between the gates and the global bit lines. Processes for fabricating the vertical TFT select devices utilize a gate dielectric and optional dielectric bases to provide isolation between the gates and bit lines.

Abstract: In a thin-film resistor stack (e.g. A ReRAM embedded resistor), a metallic barrier layer 1-5 nm thick protects an underlying or overlying ternary metal nitride layer from unwanted oxidation while having negligible effect on the resistance or height of the stack. For devices subjected to temperatures over 650 C after forming the stack, the metallic barrier layer may be iridium or ruthenium. For devices with temperatures kept below 650 C after forming the stack, the metallic barrier layer may be Al. The metallic barrier layer(s) and the ternary nitride layer may be formed in situ, for example by sputtering or atomic layer deposition.

Abstract: A resistor array for multi-bit data storage without the need to increase the size of a memory chip or scale down the feature size of a memory cell contained within the memory chip is provided. The resistor array incorporates a number of discrete resistive elements to be selectively connected, in different series combinations, to at least one memory cell or memory device. In one configuration, by connecting each memory cell or device with at least one resistor array, a resistive switching layer found in the resistive switching memory element of the connected memory device is capable of being at multiple resistance states for storing multiple bits of digital information. During device programming operations, when a desired series combination of the resistive elements within the resistor array is selected, the resistive switching layer in the connected memory device can be in a desired resistance state.

Abstract: Provided are resistive random access memory (ReRAM) cells having switching layers that include hafnium, aluminum, oxygen, and nitrogen. The composition of such layers is designed to achieve desirable performance characteristics, such as low current leakage as well as low and consistent switching currents. In some embodiments, the concentration of nitrogen in a switching layer is between about 1 and 20 atomic percent or, more specifically, between about 2 and 5 atomic percent. Addition of nitrogen helps to control concentration and distribution of defects in the switching layer. Also, nitrogen as well as a combination of two metals helps with maintaining this layer in an amorphous state. Excessive amounts of nitrogen reduce defects in the layer such that switching characteristics may be completely lost. The switching layer may be deposited using various techniques, such as sputtering or atomic layer deposition (ALD).

Abstract: Provided are resistive random access memory (ReRAM) cells and methods of fabricating thereof. The ReRAM cells may include a first layer operable as a bottom electrode and a second layer operable to switch between a first resistive state and a second resistive state. The ReRAM cells may include a third layer that includes a material having a lower breakdown voltage than the second layer and further includes a conductive path created by electrical breakdown. The third layer may include any of tantalum oxide, titanium oxide, and zirconium oxide. Moreover, the third layer may include a binary nitride or a ternary nitride. The binary nitrides may include any of tantalum, titanium, tungsten, and molybdenum. The ternary nitrides may include silicon or aluminum and any of tantalum, titanium, tungsten, and molybdenum. The ReRAM cells may further include a fourth layer operable as a top electrode.

Abstract: A three-dimensional array of memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. The memory elements can be set to a low resistance state and reset to a high resistance state during standard operation by biasing appropriate voltages on the word lines and bit lines. Prior to standard operation, the memory elements undergo a forming operation, during which current through the bit lines is limited. A forming voltage is applied to the memory elements during forming with a polarity such that a higher voltage is applied to anodes and a lower voltage to cathodes.

Abstract: Provided are resistive random access memory (ReRAM) cells and methods of fabricating thereof. A stack including a defect source layer, a defect blocking layer, and a defect acceptor layer disposed between the defect source layer and the defect blocking layer may be subjected to annealing. During the annealing, defects are transferred in a controllable manner from the defect source layer to the defect acceptor layer. At the same time, the defects are not transferred into the defect blocking layer thereby creating a lowest concentration zone within the defect acceptor layer. This zone is responsible for resistive switching. The precise control over the size of the zone and the defect concentration within the zone allows substantially improvement of resistive switching characteristics of the ReRAM cell. In some embodiments, the defect source layer includes aluminum oxynitride, the defect blocking layer includes titanium nitride, and the defect acceptor layer includes aluminum oxide.

Abstract: Methods for forming non-volatile storage elements in a non-volatile storage system are described. In some embodiments, during a forming operation, a cross-point memory array may be biased such that waste currents are minimized or eliminated. In one example, the memory array may be biased such that a first word line comb is set to a first voltage, a second word line comb interdigitated with the first word line comb is set to the first voltage, and selected vertical bit lines are set to a second voltage such that a forming voltage is applied across non-volatile storage elements to be formed. In some embodiments, a memory array may include a plurality of word line comb layers and a forming operation may be concurrently performed on non-volatile storage elements on all of the plurality of word line comb layers or a subset of the plurality of word line comb layers.

Abstract: Methods for determining memory cell states during a read operation using a detection scheme that reduces the area of detection circuitry for detecting the states of the memory cells by time multiplexing the use of portions of the detection circuitry are described. The read operation may include a precharge phase, a sensing phase, and a detection phase. In some embodiments, a first bit line and a second bit line may be precharged to a read voltage in parallel, and then sensing and/or detection of selected memory cells corresponding with the first bit line and the second bit line may be performed serially using the same detection circuitry by time multiplexing the use of the detection circuitry. In some cases, the time multiplexed detection circuitry may be used for detecting two or more states corresponding with two or more memory cells being sensed during a read operation.

Abstract: A three-dimensional array of memory elements is formed across multiple layers of planes positioned at different distances above a semiconductor substrate. The memory elements reversibly change a level of electrical conductance in response to a voltage difference being applied across them. The three-dimensional array includes a two-dimensional array of pillar lines from the substrate through the multiple layers of planes. A first set of pillar lines acts as local bit lines for accessing the memory elements together with an array of word lines on each plane. A second set of pillar lines is connected to the word lines. An array of metal lines on the substrate is switchable connected to the pillar lines to provide access to the first and second sets of pillar lines, thereby to provide access respectively to the bit lines and word lines of the three-dimensional array.

Abstract: Filament size and shape in a ReRAM stack can be controlled by doping layers of a variable-resistance stack to change the crystallization temperature. This changes the density of the grain boundaries that form during annealing and provide minimal-resistance paths for the migration of charged defects. Hf, Zr, or Ti decreases the crystallization temperature and narrows the filament, while Si or N increases the crystallization temperature and widens the filament. Tapered filaments are of interest: The narrow tip requires little energy to break and re-form, enabling the cell to operate at low power, yet the wider body and base are insensitive to entropic behavior of small numbers of defects, enabling the cell to retain data for long periods.

Abstract: A memory cell according to the present invention comprises a bottom conductor, a doped semiconductor pillar, and a top conductor. The memory cell does not include a dielectric rupture antifuse separating the doped semiconductor pillar from either conductor, or within the semiconductor pillar. The memory cell is formed in a high-impedance state, in which little or no current flows between the conductors on application of a read voltage. Application of a programming voltage programs the cell, converting the memory cell from its initial high-impedance state to a low-impedance state. A monolithic three dimensional memory array of such cells can be formed, comprising multiple memory levels, the levels monolithically formed above one another.

Abstract: Methods for determining memory cell states during a read operation using a detection scheme that reduces the area of detection circuitry for detecting the states of the memory cells by time multiplexing the use of portions of the detection circuitry are described. The read operation may include a precharge phase, a sensing phase, and a detection phase. In some embodiments, a first bit line and a second bit line may be precharged to a read voltage in parallel, and then sensing and/or detection of selected memory cells corresponding with the first bit line and the second bit line may be performed serially using the same detection circuitry by time multiplexing the use of the detection circuitry. In some cases, the time multiplexed detection circuitry may be used for detecting two or more states corresponding with two or more memory cells being sensed during a read operation.

Abstract: Embodiments of the invention generally relate to nonvolatile memory devices and methods for manufacturing such memory devices. The methods for forming improved memory devices, such as a ReRAM cells, provide optimized, atomic layer deposition (ALD) processes for forming a metal oxide film stack which contains at least one hard metal oxide film (e.g., metal is completely oxidized or substantially oxidized) and at least one soft metal oxide film (e.g., metal is less oxidized than hard metal oxide). The soft metal oxide film is less electrically resistive than the hard metal oxide film since the soft metal oxide film is less oxidized or more metallic than the hard metal oxide film. In one example, the hard metal oxide film is formed by an ALD process utilizing ozone as the oxidizing agent while the soft metal oxide film is formed by another ALD process utilizing water vapor as the oxidizing agent.

Abstract: A metal silicon oxide barrier layer between a nitride electrode containing the same metal and an oxide variable-resistance layer in a ReRAM cell prevents the metal from diffusing into the variable-resistance layer and prevents oxygen from diffusing into and oxidizing the electrode. Compound oxides of the same metal and silicon with varying stoichiometries and metal/silicon ratios may optionally replace part or all of the variable-resistance layer, a defect-reservoir layer, or both. The metal nitride electrode may include a metal silicon nitride current-limiting portion. Optionally, all the layers sharing the common metal may be formed in-situ as part of a single unit process, such as atomic layer deposition.