Patents Assigned to Sandisk 3D LLC
  • 3D Non-Volatile Memory Having Low-Current Cells and Methods
    Publication number: 20140254231
    Abstract: A 3D array of nonvolatile memory has each read/write element accessed at a crossing between a word line and a bit line. The read/write element forms a tubular electrode having an outside shell of R/W material enclosing an oxide core. In a rectangular form, one side of the electrode contacts the word line and another side contacts the bit line. The thickness of the shell rather than its surface areas in contact with the word line and bit line determines the conduction cross-section and therefore the resistance. By adjusting the thickness of the shell, independent of its contact area with either the word line or bit line, each read/write element can operate with a much increased resistance and therefore much reduced current. Processes to manufacture a 3D array with such tubular R/W elements 3D array are also described.
    Type: Application
    Filed: March 4, 2014
    Publication date: September 11, 2014
    Applicant: SanDisk 3D LLC
    Inventors: Raul Adrian Cernea, Yung-Tin Chen, George Samachisa
  • VERTICAL BIT LINE TFT DECODER FOR HIGH VOLTAGE OPERATION
    Publication number: 20140252454
    Abstract: A 3D memory array having a vertically oriented thin film transistor (TFT) selection device that has a channel extension, otherwise referred to as a gate/junction offset, is disclosed. The vertically oriented TFT selection device with channel extension serves as a vertical bit line selection device in the 3D memory array. A vertical TFT select device having a channel extension has a high breakdown voltage and low leakage current. The channel extension can be at the top junction or bottom junction of the TFT. Depending on whether the memory elements undergo a forward FORM or reverse FORM, either the bottom or top junction can have the channel extension. This provides for a high voltage junction where needed.
    Type: Application
    Filed: March 7, 2013
    Publication date: September 11, 2014
    Applicant: SANDISK 3D LLC
    Inventors: Peter Rabkin, Masaaki Higashitani
  • METHODS AND APPARATUS FOR METAL OXIDE REVERSIBLE RESISTANCE-SWITCHING MEMORY DEVICES
    Publication number: 20140252298
    Abstract: In some aspects, a memory cell is provided that includes a first conducting layer, a reversible resistance switching element above the first conducting layer, a second conducting layer above the reversible resistance switching element, and a liner disposed about a sidewall of the reversible resistance switching element. The reversible resistance switching element includes a first metal oxide material, and the liner includes the first metal oxide material. Numerous other aspects are provided.
    Type: Application
    Filed: March 10, 2013
    Publication date: September 11, 2014
    Applicant: SANDISK 3D LLC
    Inventors: Yubao Li, Chu-Chen Fu, Timothy James Minvielle, Huiwen Xu
  • ASYNCHRONOUS FIFO BUFFER FOR MEMORY ACCESS
    Publication number: 20140250260
    Abstract: An asynchronous FIFO buffer that provides data in response to requests to read a memory array is disclosed. The asynchronous FIFO buffer provides the data output within a latency tolerance. The asynchronous FIFO has a read clock input and a write clock input. The read clock input receives a read enable signal that defines how data should be clocked out. The write clock input receives a write clock that is asynchronous from the read enable signal. The asynchronous FIFO inputs data from the memory array in accordance with the write clock signal. The asynchronous FIFO outputs data in accordance with the read enable signal. Control logic may pre-fetch data from the memory array into the asynchronous FIFO prior to the read enable signal first being received.
    Type: Application
    Filed: February 28, 2014
    Publication date: September 4, 2014
    Applicant: SanDisk 3D LLC
    Inventor: Kian-Chin Alex Yap
  • Charge Pump with a Power-Controlled Clock Buffer to Reduce Power Consumption and Output Voltage Ripple
    Publication number: 20140247676
    Abstract: A charge pump system includes a charge pump that receives its clock signals, generated by an oscillator circuit, though a clock buffer. The clock buffer is power-controlled to reduce power consumption and output voltage ripple. The buffer is formed of a series of inverter that are connected to the power supply level through a clamping element, such as a transistor whose gate is controlled by a regulation signal based on feedback from the pump's output.
    Type: Application
    Filed: April 22, 2014
    Publication date: September 4, 2014
    Applicant: SanDisk 3D LLC
    Inventors: Kesheng Wang, Ali Al-Shamma
  • Vertical Bit Line Non-Volatile Memory Systems And Methods Of Fabrication
    Publication number: 20140248763
    Abstract: Three-dimensional (3D) non-volatile memory arrays having a vertically-oriented thin film transistor (TFT) select device and methods of fabricating such a memory are described. The vertically-oriented TFT may be used as a vertical bit line selection device to couple a global bit line to a vertical bit line. A select device pillar includes a body and upper and lower source/drain regions. At least one gate is separated horizontally from the select device pillar by a gate dielectric. The gates overlie the global bit lines with one or more insulating layers therebetween to provide adequate isolation between the gates and the global bit lines. Processes for fabricating the vertical TFT select devices utilize a gate dielectric and optional dielectric bases to provide isolation between the gates and bit lines.
    Type: Application
    Filed: March 4, 2014
    Publication date: September 4, 2014
    Applicant: SanDisk 3D LLC
    Inventors: Michael Konevecki, Steve Radigan, Vance Dunton, Natalie Nguyen, Luke Zhang
  • Non-volatile memory having 3D array of read/write elements with vertical bit lines and select devices and methods thereof
    Patent number: 8824183
    Abstract: A three-dimensional memory is formed as an array of memory elements that are formed across multiple layers of planes positioned at different distances above a semiconductor substrate. The memory elements reversibly change a level of electrical conductance in response to a voltage difference being applied across them. The three-dimensional array includes a two-dimensional array of pillar lines acting as local vertical bit lines through the multiple layers of planes which together with arrays of word lines on each plane are used to access the memory elements. The three-dimensional memory is formed over a CMOS substrate with an intermediate pillar select layer. The pillar select layer is formed with a plurality of pillar select devices which are switching transistors formed outside the CMOS and serve to switch selected rows of pillar lines to corresponding metal lines on the substrate.
    Type: Grant
    Filed: December 12, 2011
    Date of Patent: September 2, 2014
    Assignee: Sandisk 3D LLC
    Inventors: George Samachisa, Johann Alsmeier
  • Non-volatile memory having 3D array of read/write elements and read/write circuits and method thereof
    Patent number: 8824191
    Abstract: A three-dimensional array is especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. A two-dimensional array of bit lines to which the memory elements of all planes are connected is oriented vertically from the substrate and through the plurality of planes. During sensing, to compensate for word line resistance, a sense amplifier references a stored reference value during sensing of a memory element at a given location of the word line. A layout with a row of sense amplifiers between two memory arrays is provided to facilitate the referencing. A selected memory element is reset without resetting neighboring ones when it is subject to a bias voltage under predetermined conditions.
    Type: Grant
    Filed: August 22, 2013
    Date of Patent: September 2, 2014
    Assignee: Sandisk 3D LLC
    Inventors: George Samachisa, Luca Fasoli, Yan Li, Tianhong Yan
  • Dense arrays and charge storage devices
    Patent number: 8823076
    Abstract: There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.
    Type: Grant
    Filed: March 27, 2014
    Date of Patent: September 2, 2014
    Assignee: SanDisk 3D LLC
    Inventors: Thomas H. Lee, Vivek Subramanian, James M. Cleeves, Igor G. Kouznetzov, Mark G. Johnson, Paul Michael Farmwald
  • DIELECTRIC-BASED MEMORY CELLS HAVING MULTI-LEVEL ONE-TIME PROGRAMMABLE AND BI-LEVEL REWRITEABLE OPERATING MODES AND METHODS OF FORMING THE SAME
    Publication number: 20140241031
    Abstract: In some aspects, a memory cell is provided that includes a steering element and a memory element. The memory element includes a first conductive material layer, a first dielectric material layer disposed above the first conductive material layer, a second conductive material layer disposed above the first dielectric material layer, a second dielectric material layer disposed above the second conductive material layer, and a third conductive material layer disposed above the second dielectric material layer. One or both of the first conductive material layer and the second conductive material layer comprise a stack of a metal material layer and a highly doped semiconductor material layer. Numerous other aspects are provided.
    Type: Application
    Filed: February 28, 2013
    Publication date: August 28, 2014
    Applicant: SanDisk 3D LLC
    Inventors: Abhijit Bandyopadhyay, Tanmay Kumar, Scott Brad Herner, Christopher J. Petti, Roy E. Scheuerlein
  • RERAM FORMING WITH RESET AND ILOAD COMPENSATION
    Publication number: 20140241035
    Abstract: FORMING reversible resistivity-switching elements is described herein. The FORMING voltage may be halted if the current through the memory cell reaches some reference current. The reference current may depend on how many groups of memory cells have been FORMED. This can help to increase the accuracy of determining when to halt the FORMING voltage. After the FORMING voltage is applied, a RESET voltage may be applied to those memory cells that have a resistance that is lower than a reference resistance to raise the resistance of those memory cells. By raising the resistance, the leakage current of these memory cells when other groups are programmed may be less. This, in turn, helps to prevent FORMING of the other groups from slowing down. A reason why this helps to prevent the slowdown is that the FORMING voltage may be kept near a desired level.
    Type: Application
    Filed: February 28, 2013
    Publication date: August 28, 2014
    Applicant: SANDISK 3D LLC
    Inventor: Chang Siau
  • THREE-DIMENSIONAL NONVOLATILE MEMORY AND METHOD OF FABRICATION
    Publication number: 20140239248
    Abstract: A three-dimensional memory is provided that includes a first memory level and a second memory level monolithically formed above the first memory level. The first memory level includes a first steering element coupled in series with and vertically stacked above or below a first non-volatile state change element. The second memory level includes a second steering element coupled in series with and vertically stacked above or below a second non-volatile state change element. Other aspects are also provided.
    Type: Application
    Filed: May 6, 2014
    Publication date: August 28, 2014
    Applicant: SanDisk 3D LLC
    Inventors: Mark G. Johnson, Thomas H. Lee, Vivek Subramanian, Paul Michael Farmwald, James M. Cleeves
  • THREE DIMENSIONAL NON-VOLATILE STORAGE WITH ASYMMETRICAL VERTICAL SELECT DEVICES
    Publication number: 20140242764
    Abstract: A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.
    Type: Application
    Filed: May 3, 2014
    Publication date: August 28, 2014
    Applicant: SANDISK 3D LLC
    Inventor: Roy E. Scheuerlein
  • SMART READ SCHEME FOR MEMORY ARRAY SENSING
    Publication number: 20140241090
    Abstract: Methods for reducing variability in bias voltages applied to a plurality of memory cells during a sensing operation caused by IR drops along a word line shared by the plurality of memory cells are described. In some embodiments, IR drops along a shared word line may be reduced by reducing sensing currents associated with memory cells whose state has already been determined during a sensing operation. In one example, once a sense amplifier detects that a memory cell being sensed is in a particular state, then the sense amplifier may disable sensing of the memory cell and discharge a corresponding bit line associated with the memory cell. In some cases, a bit line voltage associated with a memory cell whose state has not already been determined during a first phase of a sensing operation may be increased during a second phase of the sensing operation.
    Type: Application
    Filed: February 22, 2013
    Publication date: August 28, 2014
    Applicant: SANDISK 3D LLC
    Inventors: Yingchang Chen, Jeffrey Koon Yee Lee
  • Memory cell that employs a selectively grown reversible resistance-switching element and methods of forming the same
    Patent number: 8816315
    Abstract: A memory cell is provided that includes a reversible resistance-switching element above a substrate. The reversible resistance-switching element includes an etched material layer that includes an oxidized layer of the etched material layer above a non-oxidized layer of the etched material layer. Numerous other aspects are provided.
    Type: Grant
    Filed: February 11, 2013
    Date of Patent: August 26, 2014
    Assignee: SanDisk 3D LLC
    Inventors: April D. Schricker, Brad Herner, Mark H. Clark
  • Resistive random access memory cells having metal alloy current limiting layers
    Patent number: 8817524
    Abstract: Provided are semiconductor devices, such as resistive random access memory (ReRAM) cells, that include current limiting layers formed from alloys of transition metals. Some examples of such alloys include chromium containing alloys that may also include nickel, aluminum, and/or silicon. Other examples include tantalum and/or titanium containing alloys that may also include a combination of silicon and carbon or a combination of aluminum and nitrogen. These current limiting layers may have resistivities of at least about 1 Ohm-cm. This resistivity level is maintained even when the layers are subjected to strong electrical fields and/or high temperature processing. In some embodiments, the breakdown voltage of a current limiting layer is at least about 8V. The high resistivity of the layers allows scaling down the size of the semiconductor devices including these layers while maintaining their performance.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: August 26, 2014
    Assignees: Intermolecular, Inc., Kabushiki Kaisha Toshiba, SanDisk 3D LLC
    Inventors: Yun Wang, Tony P. Chiang, Imran Hashim, Tim Minvielle, Dipankar Pramanik, Takeshi Yamaguchi
  • Non-volatile memory having 3D array of read/write elements with low current structures and methods thereof
    Patent number: 8817514
    Abstract: A three-dimensional array read/write (R/W) memory elements is formed across multiple layers of planes positioned at different distances above a semiconductor substrate. It is preferable to operate the R/W elements with low current and high resistive states. The resistance of these resistive states depends also on the dimension of the R/W elements and is predetermined by the process technology. A sheet electrode in series with the R/W element and a method of forming it provide another degree of freedom to adjust the resistance of the R/W memory element. The thickness of the sheet electrode is adjusted to obtain a reduced cross-sectional contact in the circuit path from the word line to the bit line. This allows the R/W memory element to have a much increased resistance and therefore to operate with much reduced currents. The sheet electrode is formed with little increase in cell size.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: August 26, 2014
    Assignee: SanDisk 3D LLC
    Inventors: George Samachisa, Johann Alsmeier
  • Set/Reset Algorithm Which Detects And Repairs Weak Cells In Resistive-Switching Memory Device
    Publication number: 20140233299
    Abstract: A resistance-switching memory cell is programmed in a set or reset operation which tests the stability of the cell. A first programming phase using program voltages which increase in magnitude or duration until a program verify test is passed. A stability test phase is then performed to evaluate a stability of the memory cell. The stability test phase determines whether the memory cell is weak and likely to transition out of the set or reset state by applying one or more disturb pulses and performing one or more stability verify tests. The disturb pulses can have a reduced magnitude or duration compared to the program voltages. If the stability test phase indicates the memory cell is not stable, a second programming phase is performed. If the stability test phase indicates the memory cell is stable, the operation is concluded.
    Type: Application
    Filed: February 21, 2013
    Publication date: August 21, 2014
    Applicant: SANDISK 3D LLC
    Inventors: Zhida Lan, Roy E. Scheuerlein, Thomas Yan
  • COMPENSATION SCHEME FOR NON-VOLATILE MEMORY
    Publication number: 20140233327
    Abstract: Methods for performing parallel voltage and current compensation during reading and/or writing of memory cells in a memory array are described. In some embodiments, the compensation may include adjusting a bit line voltage and/or bit line reference current applied to a memory cell based on a memory array zone, a bit line layer, and a memory cell direction associated with the memory cell. The compensation may include adjusting the bit line voltage and/or bit line reference current on a per memory cell basis depending on memory cell specific characteristics. In some embodiments, a read/write circuit for reading and/or writing a memory cell may select a bit line voltage from a plurality of bit line voltage options to be applied to the memory cell based on whether the memory cell has been characterized as a strong, weak, or typical memory cell.
    Type: Application
    Filed: April 16, 2014
    Publication date: August 21, 2014
    Applicant: SANDISK 3D LLC
    Inventors: Yingchang Chen, Pankaj Kalra, Chandrasekhar Gorla
  • COMPENSATION SCHEME FOR NON-VOLATILE MEMORY
    Publication number: 20140233329
    Abstract: Methods for performing parallel voltage and current compensation during reading and/or writing of memory cells in a memory array are described. In some embodiments, the compensation may include adjusting a bit line voltage and/or bit line reference current applied to a memory cell based on a memory array zone, a bit line layer, and a memory cell direction associated with the memory cell. The compensation may include adjusting the bit line voltage and/or bit line reference current on a per memory cell basis depending on memory cell specific characteristics. In some embodiments, a read/write circuit for reading and/or writing a memory cell may select a bit line voltage from a plurality of bit line voltage options to be applied to the memory cell based on whether the memory cell has been characterized as a strong, weak, or typical memory cell.
    Type: Application
    Filed: February 21, 2013
    Publication date: August 21, 2014
    Applicant: SANDISK 3D LLC
    Inventors: Yingchang Chen, Pankaj Kalra, Chandrasekhar Gorla