Abstract: Embodiments generally include a method of forming a nonvolatile memory device that contains a resistive switching memory element that has an improved device switching capacity by using multiple layers of variable resistance layers. In one embodiment, the resistive switching element comprises at least three layers of variable resistance materials to increase the number of logic states. Each variable resistance layer may have an associated high resistance state and an associated low resistance state. As the resistance of each variable resistance layer determines the digital data bit that is stored, the multiple variable resistance layers per memory element allows for additional data storage without the need to further increase the density of nonvolatile memory devices.

Abstract: Provided are radiation enhanced resistive switching layers, resistive random access memory (ReRAM) cells including these layers, as well as methods of forming these layers and cells. Radiation creates defects in resistive switching materials that allow forming and breaking conductive paths in these materials thereby improving their resistive switching characteristics. For example, ionizing radiation may break chemical bonds in various materials used for such a layer, while non-ionizing radiation may form electronic traps. Radiation power, dozing, and other processing characteristics can be controlled to generate a distribution of defects within the resistive switching layer. For example, an uneven distribution of defects through the thickness of a layer may help with lowering switching voltages and/or currents. Radiation may be performed before or after thermal annealing, which may be used to control distribution of radiation created defects and other types of defects in resistive switching layers.

Abstract: A method of forming a memory cell is provided that includes forming a steering element above a substrate, forming a material layer on the substrate, patterning and etching the material layer, and oxidizing the patterned and etched material layer to form a reversible resistance-switching material. Numerous other aspects are provided.

Abstract: Provided are methods of forming nonvolatile memory elements using atomic layer deposition techniques, in which at least two different layers of a memory element are deposited sequentially and without breaking vacuum in a deposition chamber. This approach may be used to prevent oxidation of various materials used for electrodes without a need for separate oxygen barrier layers. A combination of signal lines and resistive switching layers may be used to cap the electrodes and to minimize their oxidation. As such, fewer layers are needed in a memory element. Furthermore, atomic layer deposition allows more precise control of electrode thicknesses. In some embodiments, a thickness of an electrode may be less than 50 Angstroms. Overall, atomic layer deposition of electrodes and resistive switching layers lead to smaller thicknesses of entire memory elements making them more suitable for low aspect ratio features of advanced nodes.

Abstract: The present invention provides apparatus, methods, and systems for a memory layer layout for a three-dimensional memory. The memory layer includes a plurality of memory array blocks; a plurality of memory lines coupled to the memory array blocks; and a plurality of zia contact areas for coupling the memory layer to other memory layers in a three-dimensional memory. The memory lines extend from the memory array blocks and are formed using a sidewall defined process. The memory lines have a half pitch dimension smaller than the nominal minimum feature size capability of a lithography tool used in forming the memory lines. The zia contact areas have a dimension that is approximately four times the half pitch dimension of the memory lines. The memory lines are arranged in a pattern adapted to allow a single memory line to intersect a single zia contact area and to provide area between other memory lines for other zia contact areas. Numerous additional aspects are disclosed.

Abstract: In a fabrication process for reversible resistance-switching memory cells, a bottom electrode layer is coated with nano-particles. The nano-particles are used to etch the bottom electrode layer, forming multiple narrow, spaced apart bottom electrode structures for each memory cell. A resistance-switching material is then deposited between and above the bottom electrode structures, followed by a top electrode layer. Or, insulation is deposited between and above the bottom electrode structures, followed by planarizing and a wet etch to expose top surfaces of the bottom electrode structures, then deposition of the resistance-switching material and the top electrode layer. When the resistance state of the memory cell is switched, there is a smaller area in the bottom electrode for a current path, so the switching resistance is higher and the switching current is lower.

Abstract: Methods for operating a semiconductor memory array including dynamically adjusting control line voltages (e.g., unselected word line or unselected bit line voltages) based on one or more array conditions associated with the semiconductor memory array are described. The one or more array conditions may include a temperature associated with the semiconductor memory array or a particular number of write cycles associated with the semiconductor memory array. In some embodiments, an intermediate voltage is generated based on the one or more array conditions and applied to the unselected word lines and the unselected bit lines of the semiconductor memory array. The one or more intermediate voltages may be generated such that a first voltage difference across unselected memory cells sharing a selected word line is different from a second voltage difference across other unselected memory cells sharing a selected bit line based on the one or more array conditions.

Abstract: A reversible resistance-switching memory cell has multiple narrow, spaced apart bottom electrode structures. The raised structures can be formed by coating a bottom electrode layer with nano-particles and etching the bottom electrode layer. The raised structures can be independent or joined to one another at a bottom of the bottom electrode layer. A resistance-switching material is provided between and above the bottom electrode structure, followed by a top electrode layer. Or, insulation is provided between and above the bottom electrode structures, and the resistance-switching material and top electrode layer are above the insulation. Less than one-third of a cross-sectional area of each resistance-switching memory cell is consumed by the one or more raised structures. When the resistance state of the memory cell is switched, there is a smaller area in the bottom electrode for a current path, so the switching resistance is higher and the switching current is lower.

Abstract: There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.

Abstract: A nonvolatile memory element is disclosed comprising a first electrode, a near-stoichiometric metal oxide memory layer having bistable resistance, and a second electrode in contact with the near-stoichiometric metal oxide memory layer. At least one electrode is a resistive electrode comprising a sub-stoichiometric transition metal nitride or oxynitride, and has a resistivity between 0.1 and 10 ?cm. The resistive electrode provides the functionality of an embedded current-limiting resistor and also serves as a source and sink of oxygen vacancies for setting and resetting the resistance state of the metal oxide layer. Novel fabrication methods for the second electrode are also disclosed.

Abstract: A charge pump system includes a charge pump that receives its clock signals, generated by an oscillator circuit, though a clock buffer. The clock buffer is power-controlled to reduce power consumption and output voltage ripple. The buffer is formed of a series of inverter that are connected to the power supply level through a clamping element, such as a transistor whose gate is controlled by a regulation signal based on feedback from the pump's output.

Abstract: Methods for monitoring one or more load currents corresponding with one or more voltage regulators used during operation of a semiconductor memory are described. The one or more load currents may be due to the biasing of memory cells within a memory array or due to the presence of shorts between lines in the memory array. In some embodiments, a plurality of load currents corresponding with a plurality of voltage regulators may be monitored in real-time before and during biasing of one or more memory arrays. The plurality of load currents may be monitored using a configurable load current monitoring circuit that uses a current summation technique. The ability to monitor the plurality of load currents before performing a programming operation on a memory array allows for remapping of defective portions of the memory array and modification of programming bandwidth prior to the programming operation.

Abstract: Methods for producing RRAM resistive switching elements having reduced forming voltage include doping to create oxygen deficiencies in the dielectric film. Oxygen deficiencies in a dielectric film promote formation of conductive pathways.

Abstract: Techniques disclosed herein prevent wire flaking (collapse). One aspect is an improved way of forming wires over trenches, which may be located in a hookup region of a 3D memory array, and may be used to form electrical connections between conductive lines in the memory array and drivers. The trenches are formed between CMP dummy structures. The trenches are partially filled with a flowable oxide film, which leaves a gap in the trench that is at least as wide as the total pitch of the wires to be formed. A capping layer is formed over the flowable film. After forming a conductive layer over the dielectric layer, the conductive layer is etched to form conductive wires. Some of the capping layer, as well as the CMP dummy structures may be removed. Thus, the conductive wires may be at least temporarily supported by lines of material formed from the capping layer.

Abstract: A monolithic three-dimensional memory array is provided that includes a first memory level and a second memory level disposed above or below the first memory level. The first memory level includes a plurality of vertically oriented p-i-n diodes that each include a bottom heavily doped p type region. The second memory level includes a plurality of vertically oriented p-i-n diodes that each include a bottom heavily doped n type region. Numerous other aspects are also provided.

Abstract: Embodiments of the invention include nonvolatile memory elements and memory devices comprising the nonvolatile memory elements. Methods for forming the nonvolatile memory elements are also disclosed. The nonvolatile memory element comprises a first electrode layer, a second electrode layer, and a plurality of layers of an oxide disposed between the first and second electrode layers. One of the oxide layers has linear resistance and substoichiometric composition, and the other oxide layer has bistable resistance and near-stoichiometric composition. Preferably, the sum of the two oxide layer thicknesses is between about 20 ? and about 100 ?, and the oxide layer with bistable resistance has a thickness between about 25% and about 75% of the total thickness. In one embodiment, the oxide layers are formed using reactive sputtering in an atmosphere with controlled flows of argon and oxygen.

Abstract: There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.

Abstract: Provided are methods of forming nonvolatile memory elements including resistance switching layers. A method involves diffusing oxygen from a precursor layer to one or more reactive electrodes by annealing. At least one electrode in a memory element is reactive, while another may be inert. The precursor layer is converted into a resistance switching layer as a result of this diffusion. The precursor layer may initially include a stoichiometric oxide that generally does not exhibit resistance switching characteristics until oxygen vacancies are created. Metals forming such oxides may be more electronegative than metals forming a reactive electrode. The reactive electrode may have substantially no oxygen at least prior to annealing. Annealing may be performed at 250-400° C. in the presence of hydrogen. These methods simplify process control and may be used to form nonvolatile memory elements including resistance switching layers less than 20 Angstroms thick.

Abstract: Methods for monitoring one or more load currents corresponding with one or more voltage regulators used during operation of a semiconductor memory are described. The one or more load currents may be due to the biasing of memory cells within a memory array or due to the presence of shorts between lines in the memory array. In some embodiments, a plurality of load currents corresponding with a plurality of voltage regulators may be monitored in real-time before and during biasing of one or more memory arrays. The plurality of load currents may be monitored using a configurable load current monitoring circuit that uses a current summation technique. The ability to monitor the plurality of load currents before performing a programming operation on a memory array allows for remapping of defective portions of the memory array and modification of programming bandwidth prior to the programming operation.

Abstract: A process for forming reversible resistance-switching memory cells having resistance-switching nano-particles which provide a reduced contact area to top and bottom electrodes of the memory cells, thereby limiting a peak current. Recesses are formed in a layered semiconductor material above the bottom electrodes, and one or more coatings of nano-particles are applied. The nano-particles self-assemble in the recesses so that they are positioned in a controlled manner. A top electrode material is then deposited. In one approach, the recesses are formed by spaced-apart trenches, and the nano-particles self-assemble along the spaced-apart trenches. In another approach, the recesses for each resistance-switching memory cell are separate from one another, and the resistance-switching memory cells are pillar-shaped. The coatings can be provided in one layer, or in multiple layers which are separated by an insulation layer.