Abstract: Methods of making pillar shaped device array using a triple or quadruple exposure technique are described. A plurality of pillar shaped devices are formed arranged in a hexagonal or rectangular pattern.

Abstract: Shrinking the dimensions of PMOS or NMOS thin film transistors is limited by dopant diffusion. In these devices an undoped or lightly doped channel region is interposed between heavily doped source and drain regions. When the device is built with very short gate length, source and drain dopants will diffuse into the channel, potentially shorting it and ruining the device. A suite of innovations is described which may be used in various combinations to minimize dopant diffusion during fabrication of a PMOS or NMOS polycrystalline thin film transistor, resulting in a highly scalable thin film transistor. This transistor is particularly suitable for use in a monolithic three dimensional array of stacked device levels.

Abstract: In some aspects, a method of forming a memory circuit is provided that includes (1) forming a two-terminal memory element on a substrate between a gate layer and a first metal layer of the memory circuit; and (2) forming a CMOS transistor on the substrate, the CMOS transistor for programming the two-terminal memory element. Numerous other aspects are provided.

Abstract: A memory system includes a substrate, control circuitry on the substrate, a three dimensional memory array (above the substrate) that includes a plurality of memory cells with reversible resistance-switching elements, and a circuit for detecting the setting and resetting of the reversible resistance-switching elements. In one aspect a circuit that has one or more clock inputs is run for a predetermined number of clock cycles. The circuit generates an amount of charge over the predetermined number of clock cycles. At most the amount of charge is provided to non-volatile storage element to program the non-volatile storage element. It is determined whether the non-volatile storage element is programmed to a desired state as a result of providing at most the amount of charge to the non-volatile storage element. Techniques disclosed herein can be applied to program memory cells other than memory cells with reversible resistance-switching elements.

Abstract: In the present invention a metal oxide or nitride compound which is a wide-band-gap semiconductor abuts a silicon, germanium, or alloy of silicon and/or germanium of the opposite conductivity type to form a p-n heterojunction. This p-n heterojunction can be used to advantage in various devices. In preferred embodiments, one terminal of a vertically oriented p-i-n heterojunction diode is a metal oxide or nitride layer, while the rest of the diode is formed of a silicon or silicon-germanium resistor; for example a diode may include a heavily doped n-type silicon region, an intrinsic silicon region, and a nickel oxide layer serving as the p-type terminal. Many of these metal oxides and nitrides exhibit resistivity-switching behavior, and such a heterojunction diode can be used in a nonvolatile memory cell, for example in a monolithic three dimensional memory array.

Abstract: Methods for forming patterns having triple the line frequency of a first pattern using only a single spacer are disclosed. For example, the first pattern is formed in a first and a second material using a lithographic process. Sidewall spacers are formed from a third material adjacent to exposed sidewalls of features in the second material. The width of the features in the first pattern in the first material is reduced. For example, the width is reduced to about the target width of features in a final pattern. The width of features in the first pattern in the second material is reduced using remaining portions of the first material as a mask. A second pattern is formed based on remaining portions of the second material and the sidewall spacers. The features in the second pattern may be lines having about ? the width of lines in the first pattern.

Abstract: A storage system includes a substrate, control circuitry on the substrate, a three dimensional memory array (above the substrate) that includes a plurality of reversible resistance-switching elements, and circuits for limiting the SET current for the reversible resistance-switching elements. The memory cell is SET in a reverse biased fashion.

Abstract: Systems, methods and apparatus are disclosed for employing redundant arrays to configure non-volatile memory. The present invention may include a substrate including a plurality of memory arrays, wherein the memory arrays include a data array and at least three redundant configuration arrays. The configuration arrays may each be adapted to be programmed with identical configuration information associated with operation of the data array. Majority voting logic with an output coupled to configuration inputs of the data array and inputs coupled to each of the redundant configuration arrays may be employed. The majority voting logic may be adapted to determine a configuration for the data array based upon an outcome of a majority vote function applied to the configuration information stored in the configuration arrays. Numerous other aspects are disclosed.

Abstract: Systems, methods and apparatus are disclosed for employing redundant arrays to configure non-volatile memory. The present invention may include a substrate including a plurality of memory arrays, wherein the memory arrays include a data array and at least three redundant configuration arrays. The configuration arrays may each be adapted to be programmed with identical configuration information associated with operation of the data array. Majority voting logic with an output coupled to configuration inputs of the data array and inputs coupled to each of the redundant configuration arrays may be employed. The majority voting logic may be adapted to determine a configuration for the data array based upon an outcome of a majority vote function applied to the configuration information stored in the configuration arrays. Numerous other aspects are disclosed.

Abstract: In some aspects, a memory circuit is provided that includes (1) a two-terminal memory element formed on a substrate; and (2) a CMOS transistor formed on the substrate and adapted to program the two-terminal memory element. The two-terminal memory element is formed between a gate layer and a first metal layer of the memory circuit. Numerous other aspects are provided.

Abstract: Apparatus are described for providing an adaptive trip point detector circuit that receives an input signal at an input signal node and generates an output signal at an output signal node, the output signal changing from a first value to a second value when the input signal exceeds a trip point reference value. In particular, the trip point reference value is adjusted to compensate for variations in process or temperature.

Abstract: Methods are described for providing an adaptive trip point detector circuit that receives an input signal at an input signal node and generates an output signal at an output signal node, the output signal changing from a first value to a second value when the input signal exceeds a trip point reference value. In particular, the trip point reference value is adjusted to compensate for variations in process or temperature.

Abstract: A memory array having memory cells comprising a diode and a phase change material is reliably programmed by maintaining all unselected memory cells in a reverse biased state. Thus leakage is low and assurance is high that no unselected memory cells are disturbed. In order to avoid disturbing unselected memory cells during sequential writing, previously selected word and bit lines are brought to their unselected voltages before new bit lines and word lines are selected. A modified current mirror structure controls state switching of the phase change material.

Abstract: A method of programming a nonvolatile memory cell includes applying at least one initialization pulse having a duration of at least 1 ms, followed by applying plural programming pulses having a duration of less than 1 ms. The cell includes a steering element located in series with a storage element, and the storage element includes a carbon material.

Abstract: The embodiments described herein can be used to enable one-time or few-time programmable memories to work with existing consumer electronic devices (such as those that work with flash—an erasable, non-volatile memory) without requiring a firmware upgrade, thereby providing backwards compatibility while minimizing user impact. As such, these embodiments are a viable way to bridge one-time or few-time programmable memories with existing consumer electronic devices that have flash card slots. These embodiments also allow future consumer electronic devices to be designed without updating firmware to include a file system customized for a one-time or few-time programmable memory.

Abstract: A method is described for forming a semiconductor device comprising a bipolar transistor having a base region, an emitter region and a collector region, wherein the base region comprises polycrystalline semiconductor material formed by crystallizing silicon, germanium or silicon germanium in contact with a silicide, germanide or silicide germanide. The emitter region and collector region also may be formed from polycrystalline semiconductor material formed by crystallizing silicon, germanium or silicon germanium in contact with a silicide, germanide or silicide germanide forming metal. The polycrystalline semiconductor material is preferably silicided polysilicon, which is formed in contact with C49phase titanium silicide.

Abstract: A monolithic, three dimensional NAND string includes a first memory cell located over a second memory cell. A semiconductor active region of the first memory cell is formed epitaxially on a semiconductor active region of the second memory cell, such that a defined boundary exists between the semiconductor active region of the first memory cell and the semiconductor active region of the second memory cell.

Abstract: In some aspects, a method of forming a memory cell is provided that includes (1) forming a first conductor above a substrate; (2) forming a diode above the first conductor; (3) forming a reversible resistance-switching element above the first conductor using a selective deposition process; and (4) forming a second conductor above the diode and the reversible resistance-switching element. Numerous other aspects are provided.

Abstract: A method of making a device is disclosed including: forming a first hard mask layer over an underlying layer; forming a first imprint resist layer over the underlying layer; forming first features over the first hard mask layer by bringing a first imprint template in contact with the first imprint resist layer; forming a first spacer layer over the first features; etching the first spacer layer to form a first spacer pattern and to expose top of the first features; removing the first features; patterning the first hard mask, using the first spacer pattern as a mask, to form first hard mask features; and etching at least part of the underlying layer using the first hard mask features as a mask.

Abstract: A method of making a non-volatile memory device includes providing a substrate having a substrate surface, and forming a non-volatile memory array over the substrate surface. The non-volatile memory array includes an array of semiconductor diodes, and each semiconductor diode of the array of semiconductor diodes is disposed substantially parallel to the substrate surface.